Granted Patent B2

US 12,361,865 · App. 18/512,589 · Granted Jul 15, 2025

Inventors: JinYeong Kim (Goyang-si, KR); SeongHwan Ju (Paju-si, KR); HyeonHo Son (Goyang-si, KR)

Assignee: LG Display Co., Ltd.

G09G3/32G09G2300/0408G09G2300/0443G09G2300/0819G09G2300/0861G09G2310/02G09G2310/0286

Abstract

Claims (82)

1. A display device comprising:

a display panel including a plurality of unit pixels;

a gate driver on an upper surface of the display panel and integrated in each of the plurality of unit pixels, and

a data driver on a lower surface of the display panel, the data driver configured to supply a data signal to each of the plurality of unit pixels through a side line that is on a side surface of the display panel;

wherein each of the plurality of unit pixels is driven independently and comprises a main pixel and a redundancy pixel which emit a same color,

wherein the gate driver is configured to supply a first scan signal and a second scan signal to the main pixel and the redundancy pixel,

wherein an output timing of the first scan signal supplied to the main pixel is a same as an output timing of the first scan signal supplied to the redundancy pixel,

wherein an output timing of the second scan signal supplied to the main pixel is different from an output timing of the second scan signal supplied to the redundancy pixel,

wherein a distance between the main pixel and the redundancy pixel disposed with a boundary of the plurality of unit pixels therebetween is different from a distance between the main pixel and the redundancy pixel disposed in each of the plurality of unit pixels, and

wherein the main pixel comprises a main pixel of a first color, a main pixel of a second color, and a main pixel of a third color,

wherein the redundancy pixel comprises a redundancy pixel of the first color, a redundancy pixel of the second color, and a redundancy pixel of the third color, and

wherein the gate driver is between every two of the main pixel of the first color, the main pixel of the second color, and the main pixel of the third color and between every two of the redundancy pixel of the first color, the redundancy pixel of the second color, and the redundancy pixel of the third color.

2. The display device of claim 1 , wherein the gate driver comprises a plurality of stages, and wherein an nth stage among the plurality of stages comprises:

a scan driving circuit configured to output the first scan signal, the second scan signal, and a carry signal; and

an emission driving circuit configured to output an emission control signal,

wherein n is a natural number.

3. The display device of claim 2 , wherein the scan driving circuit comprises:

a Q-node controller configured to control a voltage of a Q-node;

a QB-node controller configured to control a voltage of a QB-node;

a carry output unit configured to output the carry signal based on the voltage of the Q-node and the voltage of the QB-node;

a first scan output unit configured to output the first scan signal based on the voltage of the Q-node and the voltage of the QB-node; and

a second scan output unit configured to output the second scan signal based on the voltage of the Q-node and the voltage of the QB-node.

4. The display device of claim 3 , wherein the Q-node controller comprises a first transistor, a second transistor, and a third transistor,

wherein in the first transistor, a carry signal or a gate start signal of an (n−1)th stage is applied to a gate electrode of the first transistor, a gate-low voltage is applied to a first electrode of the first transistor, and a second electrode of the first transistor is connected to the second transistor,

wherein in the second transistor, the carry signal or the gate start signal of the (n−1)th stage is applied to a gate electrode of the second transistor, a first electrode of the second transistor is connected to the first transistor, and a second electrode of the second transistor is connected to the Q-node, and

wherein in the third transistor, a gate electrode of the third transistor is connected to the QB-node, a gate-high voltage is applied to the first electrode of the third transistor, and a second electrode of the third transistor is connected to the Q-node.

5. The display device of claim 3 , wherein the QB-node controller comprises a fourth transistor, a fifth transistor, and an eighth transistor,

wherein in the fourth transistor, a second scan signal of an (n+1)th stage is applied to a gate electrode of the fourth transistor, a gate-low voltage is applied to a first electrode of the fourth transistor, and a second electrode of the fourth transistor is connected to the QB-node,

wherein in the fifth transistor, the carry signal or a gate start signal of an (n−1)th stage is applied to a gate electrode of the fifth transistor, a gate-high voltage is applied to a first electrode of the fifth transistor, and a second electrode of the fifth transistor is connected to the QB-node, and

wherein in the eighth transistor, a gate electrode of the eighth transistor is connected to the Q-node, the gate-high voltage is applied to a first electrode of the eighth transistor, and a second electrode of the eighth transistor is connected to the QB-node.

6. The display device of claim 3 , wherein the QB-node controller comprises a fourth transistor, a fifth transistor and an eighth transistor,

wherein in the fourth transistor, a carry signal of an (n+1)th stage is applied to a gate electrode of the fourth transistor, a gate-low voltage is applied to a first electrode of the fourth transistor, and a second electrode of the fourth transistor is connected to the QB-node,

wherein in the fifth transistor, the carry signal or a gate start signal of an (n−1)th stage is applied to a gate electrode of the fifth transistor, a gate-high voltage is applied to a first electrode of the fifth transistor, and a second electrode of the fifth transistor is connected to the QB-node, and

wherein in the eighth transistor, a gate electrode of the eighth transistor is connected to the Q-node, the gate-high voltage is applied to a first electrode of the eighth transistor, and a second electrode of the eighth transistor is connected to the QB-node.

7. The display device of claim 2 , wherein the emission driving circuit comprises a QE-node controller configured to control a voltage of a QE-node and an emission output configured to output the emission control signal based on the voltage of the QE-node.

8. The display device of claim 7 , wherein the QE-node controller comprises a tenth transistor, and an eleventh transistor,

wherein in the tenth transistor, a second scan signal of an (n+1)th stage is applied to a gate electrode of the tenth transistor, an emission-low voltage is applied to a first electrode of the tenth transistor, and a second electrode of the tenth transistor is connected to the QE-node, and

wherein in the eleventh transistor, a carry signal or a gate start signal of an (n−1)th stage is applied to a gate electrode of the eleventh transistor, an emission-high voltage is applied to a first electrode of the eleventh transistor, and a second electrode of the eleventh transistor is connected to the QE-node.

9. The display device of claim 7 , wherein the QE-node controller comprises a tenth transistor, and an eleventh transistor,

wherein in the tenth transistor, a carry signal of an (n+1)th stage is applied to a gate electrode of the tenth transistor, an emission-low voltage is applied to a first electrode of the tenth transistor, and a second electrode of the tenth transistor is connected to the QE-node, and

wherein in the eleventh transistor, a carry signal or a gate start signal of an (n−1)th stage is applied to a gate electrode of the eleventh transistor, an emission-high voltage is applied to a first electrode of the eleventh transistor, and a second electrode of the eleventh transistor is connected to the QE-node.

10. The display device of claim 2 , wherein the scan driving circuit of the nth stage applies the carry signal to a scan driving circuit and an emission driving circuit of an (n+1)th stage, and applies the second scan signal to a scan driving circuit and an emission driving circuit of an (n−1)th stage.

11. The display device of claim 2 , wherein the scan driving circuit of the nth stage applies the carry signal to a scan driving circuit and an emission driving circuit of an (n−1)th stage, and applies the carry signal to a scan driving circuit and an emission driving circuit of an (n+1)th stage.

12. The display device of claim 2 , wherein each of the main pixel and the redundancy pixel comprises a first input terminal, a second input terminal, and a third input terminal,

wherein the scan driving circuit of the nth stage applies the first scan signal to a first input terminal of an nth main pixel and a second input terminal of an nth redundancy pixel, and applies the second scan signal to a first input terminal of an nth redundancy pixel and a second input terminal of an (n+1)th main pixel, and

wherein the emission driving circuit of the nth stage applies the emission control signal to a third input terminal of the nth main pixel and a third input terminal of the nth redundancy pixel.

13. The display device of claim 12 , wherein each of the main pixel and the redundancy pixel comprises a driving transistor, a first switching transistor, a second switching transistor, an emission control transistor, a first initializing transistor and a second initializing transistor,

wherein in the first switching transistor, a data voltage is input to a first electrode of the first switching transistor, a second electrode of the first switching transistor is connected to a first node, and a first input terminal is connected to a gate electrode of the first switching transistor,

wherein in the driving transistor, a pixel-high voltage is applied to a first electrode of the driving transistor, a second electrode of the driving transistor is connected to a third node, and a gate electrode of the driving transistor is connected to a second node,

wherein in the second switching transistor, a first electrode of the second switching transistor is connected to the third node, a second electrode of the second switching transistor is connected to the second node, and a gate electrode of the second switching transistor is connected to the first input terminal,

wherein in the emission control transistor, a first electrode of the emission control transistor is connected to the third node, a second electrode of the emission control transistor is connected to a light emitting diode (LED), and a gate electrode of the emission control transistor is connected to the third input terminal,

wherein in the first initializing transistor, an initializing voltage is applied to a first electrode of the first initializing transistor, a second electrode of the first initializing transistor is connected to the third node, and a gate electrode of the first initializing transistor is connected to the second input terminal, and

wherein in the second initializing transistor, the initializing voltage is applied to a first electrode of the second initializing transistor, a second electrode of the second initializing transistor is connected to the first node and the third input terminal is connected to a gate electrode of the second initializing transistor.

14. The display device of claim 1 , wherein the first color, the second color, and the third color are different from each other and are selected from a red color, a green color, and a blue color.

15. The display device of claim 1 , wherein the redundancy pixel is configured to emit light simultaneously with the main pixel, or to emit light when a defect occurs in the main pixel.

16. A display panel, comprising:

a plurality of unit pixels; and

a gate driver integrated in each of the plurality of unit pixels, and

wherein each of the plurality of unit pixels comprises a main pixel and a redundancy pixel,

wherein the gate driver is configured to supply a first scan signal and a second scan signal to the main pixel and the redundancy pixel,

wherein an output timing of the first scan signal supplied to the main pixel is a same as an output timing of the first scan signal supplied to the redundancy pixel,

wherein an output timing of the second scan signal supplied to the main pixel is different from an output timing of the second scan signal supplied to the redundancy pixel,

wherein a distance between the main pixel and the redundancy pixel disposed with a boundary of the plurality of unit pixels therebetween is different from a distance between the main pixel and the redundancy pixel disposed in each of the plurality of unit pixels,

wherein the main pixel comprises a main pixel of a first color, a main pixel of a second color, and a main pixel of a third color,

wherein the redundancy pixel comprises a redundancy pixel of the first color, a redundancy pixel of the second color, and a redundancy pixel of the third color, and

wherein the gate driver is between every two of the main pixel of the first color, the main pixel of the second color, and the main pixel of the third color and between every two of the redundancy pixel of the first color, the redundancy pixel of the second color, and the redundancy pixel of the third color.

17. A pixel structure, comprising:

a plurality of unit pixels, each of the plurality of unit pixels including a main pixel and a redundancy pixel; and

a stage of a gate driver integrated in each of the plurality of unit pixels,

wherein the stage of the gate driver is configured to supply a first scan signal and a second scan signal to the main pixel and the redundancy pixel,

wherein an output timing of the first scan signal supplied to the main pixel is a same as an output timing of the first scan signal supplied to the redundancy pixel,

wherein an output timing of the second scan signal supplied to the main pixel is different from an output timing of the second scan signal supplied to the redundancy pixel,

wherein a distance between the main pixel and the redundancy pixel disposed with a boundary of the plurality of unit pixels therebetween is different from a distance between the main pixel and the redundancy pixel disposed in each of the plurality of unit pixels,

wherein the main pixel comprises a main pixel of a first color, a main pixel of a second color, and a main pixel of a third color,

wherein the redundancy pixel comprises a redundancy pixel of the first color, a redundancy pixel of the second color, and a redundancy pixel of the third color, and

wherein the stage of the gate driver is between every two of the main pixel of the first color, the main pixel of the second color, and the main pixel of the third color and between every two of the redundancy pixel of the first color, the redundancy pixel of the second color, and the redundancy pixel of the third color.

18. The pixel structure of claim 17 , wherein the stage of the gate driver comprises:

a scan driving circuit configured to output the first scan signal, the second scan signal and a carry signal; and

an emission driving circuit configured to output an emission control signal,

wherein the main pixel comprises a main pixel of a first color, a main pixel of a second color, and a main pixel of a third color, and the redundancy pixel comprises a redundancy pixel of the first color, a redundancy pixel of the second color, and a redundancy pixel of the third color, and

wherein the scan driving circuit is between the main pixel of the first color and the main pixel of the second color, and between the redundancy pixel of the first color and the redundancy pixel of the second color, and

wherein the emission driving circuit is between the main pixel of the second color and the main pixel of the third color and between the redundancy pixel of the second color and the redundancy pixel of the third color.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (42)