Semiconductor device
A semiconductor device includes a first terminal, a second terminal, a first chip, and a resistance part. The first chip includes a substrate electrically connected to the second terminal, a nitride semiconductor layer located on the substrate, a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal, a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal, and a substrate capacitance between the first drain electrode and the substrate. The resistance part is connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal.
1. A semiconductor device, comprising:
a first terminal;
a second terminal;
a first chip comprising:
a substrate electrically connected to the second terminal,
a nitride semiconductor layer located on the substrate,
a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal,
a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal,
a lateral main current path between the first drain electrode and the first source electrode, and
a substrate capacitance formed between the first drain electrode and the substrate without the inclusion of a separate capacitor; and
a resistor connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal, wherein a series resonance between the substrate capacitance and a parasitic inductance of one or more wires connected to the semiconductor device is absorbed by the resistor to suppress ringing of a drain current.
2. The device according to claim 1 , further comprising:
a second chip comprising:
a second source electrode electrically connected to the first source electrode of the first chip, and
a second drain electrode electrically connected to the second terminal.
3. The device according to claim 1 , wherein
the first chip includes a normally-on HEMT (High Electron Mobility Transistor), and
the second chip includes a normally-off MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
4. The device according to claim 1 , further comprising:
a die pad to which the first chip is mounted, the die pad being bonded to the substrate.
5. The device according to claim 4 , wherein the resistor includes a chip resistor electrically connected between the die pad and the second terminal.
6. The device according to claim 4 , wherein
the die pad also is used as the second terminal, and
the resistor includes a bonding member that bonds the substrate and the die pad.
7. The device according to claim 4 , wherein the resistor is located on the first chip, and is electrically connected to the die pad and the second terminal by wires.
8. The device according to claim 1 , wherein the resistor includes a resistance layer located at the substrate or the nitride semiconductor layer.
9. The device according to claim 1 , wherein the substrate is a silicon substrate.
10. The device according to claim 1 , wherein a resistance of the resistor is greater than a resistance of the substrate.