Semiconductor package and method of manufacturing semiconductor package
A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.
1. A semiconductor package, comprising:
a first die, wherein the first die comprises first bonding pads;
a second die disposed over the first die, wherein the second die comprises second bonding pads, wherein the first bonding pads are bonded to the second bonding pads, wherein the second die comprises a substrate and a plurality of through vias extending through the substrate, wherein the second die comprises a plurality of alignment marks, wherein a pitch between an adjacent two of the plurality of alignment marks is different from a pitch between an adjacent two of plurality of through vias, wherein the plurality of alignment marks extends from an upper surface of the second die, the upper surface of the second die facing away from the first die;
an encapsulating material disposed over the first die, the encapsulating material laterally encapsulating the second die; and
a redistribution structure disposed over the second die and the encapsulating material, wherein the redistribution structure comprises conductive features, wherein the conductive features are electrically connected to corresponding ones of the plurality of through vias.
2. The semiconductor package of claim 1 , wherein a depth of each of the plurality of alignment marks is different from a depth of each of the plurality of through vias.
3. The semiconductor package of claim 1 , wherein the second die further comprises an isolation layer disposed between the substrate of the second die and the redistribution structure, wherein the plurality of through vias extend through the isolation layer.
4. The semiconductor package of claim 3 , wherein the plurality of alignment marks extends from an upper surface of the isolation layer facing the redistribution structure toward the substrate.
5. The semiconductor package of claim 1 , wherein the plurality of alignment marks do not overlap with the conductive features of the redistribution structure from a top view.
6. The semiconductor package of claim 1 , wherein the redistribution structure comprises an alignment pattern overlapping the plurality of alignment marks, wherein the alignment pattern comprises a conductive material.
7. The semiconductor package of claim 1 , wherein the redistribution structure comprises a dielectric material, wherein the dielectric material of the redistribution structure and the plurality of alignment marks comprise a single continuous layer.
8. The semiconductor package of claim 1 , wherein the plurality of alignment marks comprise conductive material.
9. The semiconductor package of claim 1 , wherein the plurality of alignment marks are disposed at a corner of the second die.
10. The semiconductor package of claim 1 , wherein the plurality of alignment marks comprises a first set of alignment marks and a second set of alignment marks, wherein the first set of alignment marks and the second set of alignment marks are disposed at different corners of the second die or at different sides of the second die.
11. The semiconductor package of claim 1 , wherein the second die comprises an active region and a seal ring structure surrounding the active region of the second die, wherein the plurality of alignment marks is disposed outside the active region.
12. The semiconductor package of claim 1 , wherein a cross sectional shape of one of the plurality of alignment marks is different from a cross sectional shape of one of the plurality of through vias.
13. A semiconductor package, comprising:
a first die;
a second die disposed over and bonded to the first die, wherein the second die comprises a substrate and a plurality of through vias extending through the substrate, wherein the second die comprises a plurality of alignment marks, wherein a depth of the plurality of alignment marks is different than a depth of the plurality of through vias;
a first encapsulating material laterally encapsulating the first die and the second die; and
a first redistribution structure disposed over the second die and the first encapsulating material, wherein the first redistribution structure comprises first conductive features electrically connected to the second die, wherein the first redistribution structure directly contacts the plurality of alignment marks.
14. The semiconductor package of claim 13 , further comprising a second encapsulating material disposed over the first die and laterally encapsulating the second die, the first encapsulating material laterally encapsulating the first die and the second encapsulating material.
15. The semiconductor package of claim 14 , further comprising a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure comprises second conductive features electrically connected to the plurality of through vias, wherein the first encapsulating material laterally encapsulates the second redistribution structure, wherein the first redistribution structure is disposed over the second redistribution structure and the first encapsulating material.
16. The semiconductor package of claim 13 , further comprising a plurality of through interlayer vias extending through the first encapsulating material.
17. A semiconductor package, comprising:
a first die, wherein the first die comprises a plurality of first bonding pads;
a second die, wherein the second die comprises a plurality of second bonding pads bonded to corresponding ones of the plurality of first bonding pads, wherein the second die comprises a plurality of through vias, wherein the second die comprises:
a semiconductor substrate;
an isolation layer over the semiconductor substrate; and
a plurality of first alignment marks in the isolation layer, wherein a pitch between an adjacent two first alignment marks of the plurality of first alignment marks is different from a pitch between an adjacent two through vias of the plurality of through vias;
an encapsulating material over the first die, wherein the encapsulating material laterally encapsulates the second die, wherein a surface of the encapsulating material is level with a surface of the isolation layer; and
a redistribution structure over the second die and the encapsulating material, wherein the isolation layer is between the semiconductor substrate and the redistribution structure.
18. The semiconductor package of claim 17 , wherein the redistribution structure comprises:
a first dielectric layer over the isolation layer; and
a second alignment mark in the first dielectric layer, wherein the second alignment mark overlaps at least one of the plurality of first alignment marks.
19. The semiconductor package of claim 18 , wherein the redistribution structure further comprises:
a second dielectric layer over the first dielectric layer; and
a third alignment mark in the second dielectric layer.
20. The semiconductor package of claim 17 , wherein the plurality of first alignment marks extends through the isolation layer.