Three-dimensional integrated circuit structures
Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
1. A three-dimensional integrated circuit structure, comprising:
a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region; and
a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark, wherein the first die further comprises a plurality of first seal ring patterns within the first seal ring region and outside of the second seal ring region from a top view.
2. The three-dimensional integrated circuit structure of claim 1 , wherein the first alignment mark is within the second seal ring region from a top view.
3. The three-dimensional integrated circuit structure of claim 1 , wherein the second die further comprises a plurality of second seal ring patterns within the second seal ring region and surrounding the second alignment mark.
4. The three-dimensional integrated circuit structure of claim 1 , wherein the first die further has a first interconnect structure, and a first top metal feature of the first interconnect structure is at a level substantially the same as that of the first alignment mark.
5. The three-dimensional integrated circuit structure of claim 1 , wherein the second die further has a second interconnect structure, and a second top metal feature of the second interconnect structure is at a level substantially the same as that of the second alignment mark.
6. The three-dimensional integrated circuit structure of claim 1 , wherein each of the first alignment mark and the second alignment mark is square, rectangular, polygonal, round, elliptical, strip-shaped, T-shaped, L-shaped, box-shaped or cross-shaped.
7. The three-dimensional integrated circuit structure of claim 1 , wherein the second die is bonded to the first die through a hybrid bonding comprising a metal-to-metal bonding and a dielectric-to-dielectric bonding.
8. The three-dimensional integrated circuit structure of claim 3 , wherein the first alignment mark and the first seal ring patterns are at substantially the same level.
9. The three-dimensional integrated circuit structure of claim 3 , wherein the second alignment mark and the second seal ring patterns are at substantially the same level.
10. The three-dimensional integrated circuit structure of claim 1 , wherein the first die further comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and the first alignment mark is over the first semiconductor substrate and aside the first interconnect structure.
11. The three-dimensional integrated circuit structure of claim 10 , wherein the first die further comprises a first bonding structure over the first interconnect structure, and the first bonding structure comprises a plurality of first bonding features embedded by at least one first bonding dielectric layer.
12. The three-dimensional integrated circuit structure of claim 1 , wherein the second die further comprises a second semiconductor substrate, a second interconnect structure over the second semiconductor substrate, and the second alignment mark is over the second semiconductor substrate and aside the second interconnect structure.
13. The three-dimensional integrated circuit structure of claim 12 , wherein the second die further comprises a second bonding structure over the second interconnect structure, and the second bonding structure comprises a plurality of second bonding features embedded by at least one second bonding dielectric layer.
14. The three-dimensional integrated circuit structure of claim 1 , wherein the first alignment mark and the second alignment mark are within a corner of the second seal ring region of the second die from a top view.
15. The three-dimensional integrated circuit structure of claim 1 , further comprising a plurality of through dielectric vias over the first die and surrounding the second die.
16. The three-dimensional integrated circuit structure of claim 15 , further comprising a redistribution layer structure over the second die and electrically connected to the plurality of through dielectric vias.
17. The three-dimensional integrated circuit structure of claim 1 , wherein from a top view, the first alignment mark comprises a shape complementary of a shape of the second alignment mark.
18. A three-dimensional integrated circuit structure, comprising:
a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region; and
a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark,
wherein the first alignment mark is between metal features of a first interconnect structure of the first die, and the second alignment mark is outside of metal features of a second interconnect structure of the second die.
19. A three-dimensional integrated circuit structure, comprising:
a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region;
a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark; and
a plurality of through dielectric vias over the first die and surrounding the second die,
wherein the first die further comprises a plurality of first seal ring patterns at an outer side of the through dielectric vias.