Semiconductor integrated circuit, semiconductor device and method for aligning semiconductor integrated circuits

1 . A semiconductor integrated circuit, comprising:

a substrate; and

an overlay mark structure in the substrate and comprising first overlay marks and second overlay marks separated from each other,

wherein a first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks,

wherein the overlay mark structure further comprises third overlay marks separated from each other, a third mark width of the third overlay marks is smaller than the second mark width of the second overlay marks,

the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the third overlay marks are arranged along the first direction,

the second overlay marks are between the first overlay marks and the third overlay marks.

2 . The semiconductor integrated circuit according to claim 1 , wherein the overlay mark structure further comprises fourth overlay marks separated from each other and arranged along a second direction perpendicular to the first direction, a fourth mark width of the fourth overlay marks is smaller than the second mark width of the second overlay marks, and the second overlay marks are between the first overlay marks and the fourth overlay marks.

3 . A semiconductor integrated circuit, comprising:

a substrate; and

an overlay mark structure in the substrate and comprising first overlay marks and second overlay marks separated from each other,

wherein a first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks,

the overlay mark structure further comprises fifth overlay marks separated from each other, the first mark width of the first overlay marks is smaller than a fifth mark width of the fifth overlay marks,

the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the fifth overlay marks are arranged along the first direction,

the first overlay marks are between the second overlay marks and the fifth overlay marks.

4 . The semiconductor integrated circuit according to claim 3 , wherein the overlay mark structure further comprises sixth overlay marks separated from each other and arranged along a second direction perpendicular to the first direction, the first mark width of the first overlay marks is smaller than a sixth mark width of the sixth overlay marks, and the first overlay marks are between the second overlay marks and the sixth overlay marks.

5 . A semiconductor device, comprising:

a first semiconductor wafer comprising a first overlay mark structure, wherein the first overlay mark structure comprises a first overlay mark and a second overlay mark separated from each other, a first mark width of the first overlay mark is smaller than a second mark width of the second overlay mark; and

a second semiconductor wafer bonded to the first semiconductor wafer along a first direction and comprising a second overlay mark structure, wherein the second overlay mark structure comprises a third overlay mark, the third overlay mark at least partially overlaps the first overlay mark of the first semiconductor wafer along the first direction.

6 . The semiconductor device according to claim 5 , wherein a third mark width of the third overlay mark of the second semiconductor wafer is larger than the first mark width of the first overlay mark of the first semiconductor wafer.

7 . The semiconductor device according to claim 5 , wherein the first overlay mark of the first semiconductor wafer directly contacts the third overlay mark of the second semiconductor wafer.

8 . The semiconductor device according to claim 5 , wherein the first semiconductor wafer further comprises a first substrate, the first overlay mark structure is in the first substrate, the second semiconductor wafer further comprises a second substrate, the second overlay mark structure is in the second substrate, and the second overlay mark of the first semiconductor wafer directly contacts the second substrate of the second semiconductor wafer.

9 . The semiconductor device according to claim 8 , wherein the third overlay mark of the second semiconductor wafer directly contacts the first overlay mark and the first substrate of the first semiconductor wafer.