IP Library › Granted Patent US 12,366,708
Granted Patent B2
US 12,366,708 · App. 18/082,520 · Granted Jul 22, 2025

Photonic integrated circuit

Inventors: Vimal Kumar Kamineni (Fremont, CA); Matteo Staffaroni (San Ramon, CA); Faraz Najafi (Palo Alto, CA); Ann Melnichuk (Rio Rancho, NM); George Kovall (Palo Alto, CA); Yong Liang (Niskayuna, NY)
Assignee: Psiquantum, Corp.
G02B6/136G02B6/122G02B6/132
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Quick Facts
Patent No.
US 12,366,708
App. No.
18/082,520
Granted
Jul 22, 2025
Kind
B2
Abstract

A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.

Claims (50)

1. A device comprising:

a substrate;

a dielectric layer on the substrate;

a waveguide within the dielectric layer;

a heater disposed in the dielectric layer;

a thermal isolation structure including a trench in the dielectric layer and an undercut in the substrate; and

a photodetector disposed above the waveguide and monolithically integrated with the substrate, the photodetector optically coupled to the waveguide and configured to operate at temperatures below 50 K.

2. The device of claim 1 , wherein the heater is disposed proximate to the waveguide and configured to thermally tune a portion of the waveguide.

3. The device of claim 2 , wherein the waveguide and the heater form a single photon generator, a ring oscillator, an optical filter, an optical switch, or an optical interferometer.

4. The device of claim 2 , wherein the thermal isolation structure surrounds the heater.

5. The device of claim 4 , wherein the undercut extends horizontally in the substrate and is under the portion of the waveguide.

6. The device of claim 4 , wherein the trench and the undercut form a vacuum region.

7. The device of claim 4 , further comprising a cooling structure disposed to be in thermal contact with the substrate, wherein the undercut is disposed between the heater and the cooling structure.

8. The device of claim 1 , further comprising a plurality of light isolation structures in at least one of the substrate or the dielectric layer, the plurality of light isolation structures configured to prevent photons from reaching the photodetector other than through the waveguide.

9. The device of claim 8 , wherein the plurality of light isolation structures includes at least one of:

a metal trench in the dielectric layer and partially extending into the substrate;

a metal trench in the dielectric layer;

an array of metal vias in the dielectric layer;

a metal cover in the dielectric layer and on top of the photodetector; or

a deep trench in the substrate, the deep trench including an air gap or filled with a reflective or absorptive material.

10. The device of claim 9 , wherein the metal cover is in a metal layer and is aligned with or coupled to the metal trench or the array of metal vias to form a contiguous structure surrounding the photodetector.

11. The device of claim 9 , wherein:

the waveguide includes an input port; and

the metal trench or the array of metal vias is located at a region including the input port.

12. The device of claim 1 , wherein the photodetector includes a superconducting nanowire single photon detector.

13. A method comprising:

receiving a wafer, the wafer including:

a substrate,

a dielectric layer on the substrate;

a waveguide formed in the dielectric layer;

a heating structure disposed in the dielectric layer;

a thermal isolation structure including a trench in the dielectric layer and an undercut in the substrate; and

a photodetector in the dielectric layer and coupled to the waveguide;

etching the trench in the dielectric layer to expose a first portion of the substrate, the trench surrounding the photodetector;

etching, through the trench, the substrate to form the undercut in the substrate; and

filling the trench and the undercut with a light reflective or light absorptive material.

14. The method of claim 13 , wherein the heating structure is configured to thermally tune a portion of the waveguide.

15. The method of claim 14 , further comprising:

etching a third set of vias or a third trench in the dielectric layer to expose a second portion of the substrate, the third set of vias or the third trench surrounding the heating structure;

etching, through the third set of vias or the third trench, the substrate to form an undercut in the substrate, the undercut positioned below the second portion of the waveguide; and

depositing an oxide layer on the dielectric layer to seal the third set of vias or the third trench and the undercut.

16. The method of claim 14 , further comprising:

etching the dielectric layer to form contact holes for the heating structure; and

filling the contact holes with a conducting material to form electrical contacts for the heating structure.

17. The method of claim 13 , further comprising, before the filling, forming an oxide liner layer in the second set of vias or the second trench and depositing a barrier and seed layer on the oxide liner layer.

18. The method of claim 13 , further comprising forming a top metal cover on the dielectric layer and on top of the photodetector.

19. The method of claim 13 , further comprising:

etching the dielectric layer to form contact holes for the photodetector; and

filling the contact holes with a conducting material to form electrical contacts for the photodetector.

20. The method of claim 19 , wherein filling the contact holes comprises depositing a liner layer including tungsten, tungsten carbide, or tungsten nitride on sidewalls of the contact holes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2022
From: KAMINENI, VIMAL KUMAR; STAFFARONI, MATTEO; NAJAFI, FARAZ; MELNICHUK, ANN; KOVALL, GEORGE; LIANG, YONG
To: PSIQUANTUM, CORP.
Reel/Frame 062129/0707 →
Continuity (3)
Continuation PCTUS2021037422 · Jun 15, 2021
Provisional Application 63039840 · Jun 16, 2020
Related Publication 20230123000A1 · Apr 20, 2023
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