Method of fabricating electronic apparatus having contact holes penetrating at least one different insulating layer in different regions
A method of fabricating an electronic apparatus including the steps of forming a circuit element on a base substrate, forming a signal line on the base substrate, forming a first insulating layer covering the circuit element and the signal line, forming a display device layer including a light-emitting device on the first insulating layer, forming a first conductive layer on the display device layer, forming a second insulating layer covering the first insulating layer and the first conductive layer, forming a first contact hole penetrating the first and second insulating layers in a first region overlapping with the first conductive layer, forming a second contact hole penetrating the first and second insulating layers in a second region overlapping with an end portion of the signal line, forming a second conductive layer overlapping with the first region, and forming a pad overlapping with the second region.
1. A method of fabricating an electronic apparatus, the method comprising:
forming a circuit element on a base substrate;
forming a signal line on the base substrate;
forming a first insulating layer covering the circuit element and the signal line;
forming a display device layer on the first insulating layer, the display device layer comprising a light-emitting device;
forming a first conductive layer on the display device layer;
forming a second insulating layer covering the first insulating layer and the first conductive layer;
forming a first contact hole in a first region overlapping with the first conductive layer, the first contact hole penetrating the second insulating layer;
forming a second contact hole in a second region overlapping with an end portion of the signal line, the second contact hole penetrating the first and second insulating layers;
forming a second conductive layer overlapping with the first region; and
forming a pad overlapping with the second region.
2. The method of claim 1 , wherein:
forming the circuit element comprises:
forming a semiconductor pattern; and
forming a gate overlapping with the semiconductor pattern; and
the gate is formed along with the signal line.
3. The method of claim 1 , wherein:
forming the circuit element comprises:
forming a first conductive pattern of a capacitor; and
forming a second conductive pattern of the capacitor; and
the first conductive pattern or the second conductive pattern is formed along with the signal line.
4. The method of claim 1 , wherein:
the second conductive layer comprises sensing patterns; and
the second conductive layer is formed along with the pad.
5. The method of claim 1 , wherein the first contact hole is formed along with the second contact hole.
6. The method of claim 1 , further comprising:
forming, after forming the first insulating layer, a third contact hole in a third region overlapping with the circuit element; and
reducing, after forming the first insulating layer, a thickness of the first insulating layer in a fourth region overlapping with the second region.
7. The method of claim 6 , wherein:
the third contact hole and reduction of the thickness of the first insulating layer are concurrently performed;
the third contact hole is formed by etching the third region of the first insulating layer utilizing a full-tone mask; and
a fourth contact hole is formed by etching the fourth region of the first insulating layer utilizing a half-tone mask.