Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.
1. A semiconductor structure, comprising:
a base, wherein the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region;
a first gate layer surrounding the vertical transistor structure and extending along a first direction;
a second gate layer surrounding the vertical transistor structure and extending along the first direction, wherein the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and
an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer;
wherein the electrical connection structure comprises: a conductive pillar and a conductive layer, the conductive pillar has one end electrically connected to at least one of the first gate layer or the second gate layer, and the other end electrically connected to conductive layer, the conductive pillar comprises: a connecting pillar and a protective layer surrounding a sidewall of the connecting pillar, and the conductive pillar and the protective layer are made of different materials.
2. The semiconductor structure according to claim 1 , wherein the electrical connection structure comprises:
a first electrical connection structure electrically connected to the first gate layer extending to the peripheral region; and
a second electrical connection structure electrically connected to the second gate layer extending to the peripheral region, wherein the first electrical connection structure and the second electrical connection structure are disposed at intervals.
3. The semiconductor structure according to claim 2 , wherein the array region has a first side and a second side that are opposite to each other, the first electrical connection structure is located in the peripheral region close to the first side, and the second electrical connection structure is located in the peripheral region close to the second side.
4. The semiconductor structure according to claim 2 , wherein the array region has a first side and a second side that are opposite to each other, and the first electrical connection structure and the second electrical connection structure are both located in the peripheral region close to the first side or the second side.
5. The semiconductor structure according to claim 1 , wherein along the first direction, a length of the first gate layer in the peripheral region is not the same as a length of the second gate layer in the peripheral region.
6. The semiconductor structure according to claim 1 , wherein one first gate layer and one second gate layer are electrically connected to a same electrical connection structure, and the first gate layer and the second gate layer that are electrically connected to the same electrical connection structure are located in a same gap between adjacent two of the vertical transistor structures.
7. The semiconductor structure according to claim 6 , wherein the electrical connection structure comprises: a conductive pillar and a conductive layer, the conductive pillar extends along a direction perpendicular to a top surface of the base, the conductive pillar has one end electrically connected to the first gate layer, and the other end electrically connected to the conductive layer, and the conductive pillar penetrates through the second gate layer.
8. The semiconductor structure according to claim 6 , wherein the electrical connection structure comprises: a first conductive pillar and a conductive layer, wherein the first conductive pillar has one end electrically connected to the first gate layer, and the other end electrically connected to the conductive layer; and a second conductive pillar, having one end electrically connected to the first gate layer, and the other end electrically connected to the second gate layer, wherein the second conductive pillar and the first conductive pillar are disposed at intervals.
9. The semiconductor structure according to claim 1 , wherein the base in the array region further comprises bit lines arranged at intervals, the bit line extends along a second direction, the vertical transistor structure is located on a partial top surface of the bit line, in a direction perpendicular to the top surface of the bit line, the vertical transistor structure comprises a first region, a second region, and a third region that are arranged sequentially, and the first direction and the second direction are different; and
the semiconductor structure further comprises: a dielectric layer located between adjacent two of the bit lines and on a sidewall of the vertical transistor structure, the first gate layer surrounds the dielectric layer in the second region, and the second gate layer surrounds the dielectric layer in the third region.
10. The semiconductor structure according to claim 9 , further comprising: an electrical connection layer covering a top surface of the third region and extending to a partial sidewall of the vertical transistor structure, wherein the electrical connection layer and the dielectric layer jointly cover a surface of the vertical transistor structure.
11. The semiconductor structure according to claim 10 , wherein orthographic projection of the electrical connection layer on the bit line is not overlapped with or partially overlapped with orthographic projection of the second gate layer on the bit line.
12. The semiconductor structure according to claim 9 , further comprising: an insulating layer located between adjacent vertical transistor structures on a same bit line, wherein the insulating layer isolates the first gate layer and the second gate layer on adjacent dielectric layers.
13. The semiconductor structure according to claim 12 , further comprising a metal-semiconductor compound structure at least located in a bit line opposite to a bottom of the insulating layer.