Vertical semiconductor device and method for fabricating the same
A method for fabricating a vertical semiconductor device may include forming a lower-level stack including a source sacrificial layer over a semiconductor substrate; forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack; forming a vertical channel structure including a channel layer that penetrates the upper-level stack and the lower-level stack; forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer; forming a lateral recess that extends from the slit by removing the source sacrificial layer; forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess; selectively forming a second contact layer over an exposed surface of the first contact layer; and selectively forming a chemical barrier layer over the second contact layer.
1. A method for fabricating a vertical semiconductor device, comprising:
forming a lower-level stack including a source sacrificial layer over a semiconductor substrate;
forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack;
forming a vertical channel structure including a channel layer and a memory layer that penetrates the upper-level stack and the lower-level stack;
forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer;
forming a lateral recess that extends from the slit by removing the source sacrificial layer, wherein the forming the lateral recess forms vertically-extending undercuts in the memory layer, at least one of the vertically-extending undercuts extending into the source sacrificial layer over the semiconductor substrate;
forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess and while filling the vertically-extending undercuts;
selectively forming a second contact layer over an exposed surface of the first contact layer; and
selectively forming a chemical barrier layer over the second contact layer.
2. The method of claim 1 , wherein the selectively forming of the second contact layer includes:
selectively growing a polysilicon layer from the exposed surface of the first contact layer.
3. The method of claim 2 , wherein the polysilicon layer includes voids while filling a bottom portion of the slit.
4. The method of claim 1 , wherein the forming of the first contact layer includes:
depositing a polysilicon layer to fill the lateral recess; and
forming an exposed surface for growing the second contact layer over the deposited polysilicon layer, and
wherein the deposited polysilicon layer includes a plurality of voids.
5. The method of claim 1 , wherein the selectively forming of the chemical barrier layer over the second contact layer includes:
selectively depositing silicon oxide over a surface of the second contact layer.
6. The method of claim 5 , wherein the second contact layer includes a polysilicon layer, and
the chemical barrier layer includes a silicon oxide.
7. The method of claim 1 , further comprising:
replacing the sacrificial layers of an upper-level stack with gate electrodes, after the selectively forming of the chemical barrier layer over the second contact layer.
8. The method of claim 1 , wherein the second contact layer conformally covers the exposed surface of the first contact layer.
9. The method of claim 8 , wherein the selectively forming of the chemical barrier layer over the second contact layer includes:
forming silicon oxide by selectively oxidizing the surface of the second contact layer.
10. The method of claim 1 , further comprising:
forming supporters penetrating the lower-level stack after forming the lower-level stack.