Three-dimensional memory device having nitrided direct source strap contacts and method of making thereof
A lower source-level semiconductor layer, a sacrificial semiconductor layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. An array of memory stack structures containing vertical semiconductor channels that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer is formed. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the sacrificial semiconductor layer. A doped source contact layer is formed on each of the vertical semiconductor channels in the source cavity. A silicon nitride liner is formed on the doped source contact layer. The sacrificial material layers are replaced with electrically conductive layers. A dielectric wall structure is formed in the backside trench.
1. A three-dimensional memory device comprising:
source-level material layers located over a substrate and including a lower source-level semiconductor layer comprising a first semiconductor material, an upper source-level semiconductor layer comprising a second semiconductor material, and a doped source contact layer comprising a third doped semiconductor material and contacting the lower source-level semiconductor layer and the upper source-level semiconductor layer;
an alternating stack of electrically conductive layers and insulating layers located over the source-level material layers;
an array of memory stack structures that extend through the alternating stack and at least down to the doped source contact layer, each memory stack structure including a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, wherein the doped source contact layer contacts an outer sidewall of each of the vertical semiconductor channels;
a dielectric wall structure vertically extending through each layer within the alternating stack and extending below an interface between the doped source contact layer and the upper source-level semiconductor layer; and
a silicon nitride liner located between the doped source contact layer and the dielectric wall structure, wherein the silicon nitride liner is located entirely between a first horizontal plane including a planar bottom surface of the lower source-level semiconductor layer and a second horizontal plane including a planar top surface of the upper source-level semiconductor layer.
2. The three-dimensional memory device of claim 1 , wherein the silicon nitride liner directly contacts a top surface of the lower source level semiconductor layer.
3. The three-dimensional memory device of claim 1 , wherein the lower portion of the dielectric wall structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the dielectric wall structure.
4. The three-dimensional memory device of claim 3 , further comprising a silicon oxide liner located between the silicon nitride liner and the dielectric wall structure.
5. The three-dimensional memory device of claim 4 , wherein a lower portion of the dielectric wall structure comprises:
an upper tapered surface underlying an upper portion of the silicon oxide liner; and
a lower tapered surface overlying a lower portion of the silicon oxide liner.
6. The three-dimensional memory device of claim 1 , wherein the silicon nitride layer is located entirely between a horizontal plane including a top surface of the doped source contact layer and a horizontal plane including a bottom surface of the doped source contact layer.
7. The three-dimensional memory device of claim 1 , further comprising a source-level dielectric core contacting the silicon nitride liner and the dielectric wall structure.
8. The three-dimensional memory device of claim 7 , wherein the silicon nitride layer comprises:
an upper silicon nitride portion contacting a top surface of the source-level dielectric core;
a lower silicon nitride portion contacting a bottom surface of the source-level dielectric core; and
a vertical silicon nitride portion adjoining the upper silicon nitride portion and the lower silicon nitride portion.
9. The three-dimensional memory device of claim 7 , wherein:
the silicon nitride liner is laterally spaced from the dielectric wall structure; and
the source-level dielectric core contacts the dielectric wall structure.
10. A three-dimensional memory device of comprising:
source-level material layers located over a substrate and including a lower source-level semiconductor layer comprising a first semiconductor material, an upper source-level semiconductor layer comprising a second semiconductor material, and a doped source contact layer comprising a third doped semiconductor material and contacting the lower source-level semiconductor layer and the upper source-level semiconductor layer;
an alternating stack of electrically conductive layers and insulating layers located over the source-level material layers;
an array of memory stack structures that extend through the alternating stack and at least down to the doped source contact layer, each memory stack structure including a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, wherein the doped source contact layer contacts an outer sidewall of each of the vertical semiconductor channels;
a dielectric wall structure vertically extending through each layer within the alternating stack and extending below an interface between the doped source contact layer and the upper source-level semiconductor layer; and
a silicon nitride liner located between the doped source contact layer and the dielectric wall structure;
wherein:
the source-level material layers further comprise a source-level dielectric layer overlying the upper source-level semiconductor layer and contacting the dielectric wall structure, and a source-select-gate semiconductor layer overlying the source-level dielectric layer; and
a source-select-gate semiconductor oxide spacer comprising an oxide of a semiconductor material of the source-select-gate semiconductor layer is located between the source-select-gate semiconductor layer and the dielectric wall structure.
11. The three-dimensional memory device of claim 10 , further comprising an upper source-level semiconductor oxide spacer comprising an oxide of the second semiconductor material of the upper source-level semiconductor layer and contacting the upper source-level semiconductor layer and the dielectric wall structure.