IP Library › Granted Patent US 12,615,771
Granted Patent B2
US 12,615,771 · App. 17/953,009 · Granted Apr 28, 2026

Method of manufacturing semiconductor device

Inventor: Min Young Heo (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B43/27H10B41/27H10B41/30H10B43/30H10B63/84
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Quick Facts
Patent No.
US 12,615,771
App. No.
17/953,009
Granted
Apr 28, 2026
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a preliminary source structure including a source sacrificial layer and an upper source layer, forming a hole in the preliminary source structure, forming a preliminary memory layer on a surface of the hole, forming a channel layer on the preliminary memory layer, forming a trench passing through the upper source layer, forming a first buffer pattern by performing a surface treatment on a side portion of the upper source layer exposed by the trench, forming a cavity exposing a portion of the preliminary memory layer by removing the source sacrificial layer, forming an expanded cavity exposing a portion of the channel layer by removing the portion of the preliminary memory layer, and forming a source layer in the expanded cavity.

Claims (21)

1 . A method of manufacturing a semiconductor device, the method comprising:

forming a preliminary source structure including a lower source layer, a first source protective layer, a source sacrificial layer, a second source protective layer and an upper source layer;

forming a stack structure including first material layers and second material layers, the first material layers and the second material layers alternately stacked over the preliminary source structure,

forming a hole passing through the stack structure and the preliminary source structure;

forming a preliminary memory layer on a surface of the hole;

forming a channel layer on the preliminary memory layer;

forming a trench passing through the stack structure and the upper source layer;

forming a first buffer pattern and second buffer patterns by performing a surface treatment on a side portion of the upper source layer and side portions of the second material layers exposed by the trench, wherein a portion of the upper source layer remains between the first buffer pattern and the preliminary memory layer, and wherein portions of the second material layers remain between the second buffer patterns and the preliminary memory layer;

forming a preliminary buffer layer covering the first buffer pattern, the first material layers and the second buffer patterns;

removing a portion of the second source protective layer exposed by the trench;

forming a buffer layer covering the first buffer pattern, the first material layers and the second buffer patterns by performing an oxidation process of the preliminary buffer layer, wherein a dummy pattern is formed by oxidizing a portion of the source sacrificial layer;

removing a portion of the dummy pattern to expose a remaining portion of the source sacrificial layer;

forming a cavity exposing a portion of the preliminary memory layer by removing the source sacrificial layer and the first and second source protective layers;

forming an expanded cavity exposing a portion of the channel layer by removing the portion of the preliminary memory layer; and

forming a source layer in the expanded cavity.

2 . The method of claim 1 , wherein the source sacrificial layer includes nitride.

3 . The method of claim 1 , wherein the surface treatment is an oxidation process.

4 . The method of claim 1 , wherein the first buffer pattern, the second buffer patterns, the dummy pattern, the first source protective layer and the second source protective layer include oxide, and

the first buffer pattern, the second buffer patterns and the dummy pattern are removed while removing the first and second protective layers and the portion of the preliminary memory layer.

5 . The method of claim 4 , further comprising:

replacing the second material layers with conductive patterns through the trench after forming the source layer in the expanded cavity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2022
From: HEO, MIN YOUNG
To: SK HYNIX INC.
Reel/Frame 061217/0440 →
Priority Claims (1)
KR 10-2020-0068100 · Jun 5, 2020 · national
Continuity (2)
Continuation In Part 17090735 · Nov 5, 2020
Related Publication 20230020017A1 · Jan 19, 2023
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