IP Library › Granted Patent US 12,432,924
Granted Patent B2
US 12,432,924 · App. 18/218,496 · Granted Sep 30, 2025

Integrated circuitry and method used in forming a memory array comprising strings of memory cells

Inventors: John D. Hopkins (Meridian, ID); Alyssa N. Scarbrough (Boise, ID)
Assignee: Micron Technology, Inc.
H10B43/27H01L21/31116H10B43/10
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Quick Facts
Patent No.
US 12,432,924
App. No.
18/218,496
Granted
Sep 30, 2025
Kind
B2
Abstract

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.

Claims (18)

1. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line; and

a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating first insulating tiers and second insulating tiers, the lower portion comprising:

a lowest insulator tier directly above conductor material of a conductor tier, the lowest insulator tier comprising solid carbon and nitrogen-containing material; and

an immediately-adjacent tier directly above the solid carbon and nitrogen-containing material of the lowest insulator tier, the immediately-adjacent tier comprising material that is of different composition from that of the lowest insulator tier.

2. The integrated circuitry of claim 1 wherein the solid carbon and nitrogen-containing material comprises carbon-doped silicon nitride.

3. The integrated circuitry of claim 2 wherein carbon content of the carbon-doped silicon nitride is 1 to 30 atomic percent.

4. The integrated circuitry of claim 3 wherein the carbon content of the carbon-doped silicon nitride is 5 to 25 atomic percent.

5. The integrated circuitry of claim 4 wherein the carbon content of the carbon-doped silicon nitride is 10 to 15 atomic percent.

6. The integrated circuitry of claim 1 wherein the solid carbon and nitrogen-containing material comprises C 3 N 4 .

7. The integrated circuitry of claim 1 comprising a next-lowest insulator tier directly above the immediately-adjacent tier, the next-lowest insulator tier comprising the solid carbon and nitrogen-containing material.

8. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line; and

a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating first insulating tiers and second insulating tiers, the lower portion comprising:

a lowest insulator tier directly above conductor material of a conductor tier, the lowest insulator tier comprising solid carbon and nitrogen-containing material;

an immediately-adjacent tier directly above the solid carbon and nitrogen-containing material of the lowest insulator tier, the immediately-adjacent tier comprising material that is of different composition from that of the lowest insulator tier;

a next-lowest insulator tier directly above the immediately-adjacent tier, the next-lowest insulator tier comprising the solid carbon and nitrogen-containing material; and

a conducting-material tier comprising conducting material directly above the immediately-adjacent tier.

Continuity (3)
Division 17030751 · Sep 24, 2020
Provisional Application 63070979 · Aug 27, 2020
Related Publication 20230363163A1 · Nov 9, 2023
References Cited (20)
US 6844227B2 · Kubo et al. · 2005 [cited by applicant]
US 10236301B1 · Howder et al. · 2019 [cited by applicant]
US 10720445B1 · Shimizu et al. · 2020 [cited by applicant]
US 20050255642A1 · Liu et al. · 2005 [cited by applicant]
US 20100248485A1 · Block et al. · 2010 [cited by applicant]
US 20150179936A1 · Schubert et al. · 2015 [cited by applicant]
US 20150318301A1 · Lee et al. · 2015 [cited by applicant]
US 20160315095A1 · Sel et al. · 2016 [cited by applicant]
US 20170301685A1 · Dorhout et al. · 2017 [cited by applicant]
US 20180261671A1 · Matsumoto et al. · 2018 [cited by applicant]
US 20180269221A1 · Oda et al. · 2018 [cited by applicant]
US 20180323213A1 · Arai · 2018 [cited by examiner]
US 20190067306A1 · Fang et al. · 2019 [cited by applicant]
US 20190157294A1 · Kanamori et al. · 2019 [cited by applicant]
US 20200111796A1 · Nourbakhsh et al. · 2020 [cited by applicant]
US 20210135108A1 · Park et al. · 2021 [cited by applicant]
KR 1020150126524 · 2015 [cited by applicant]
WO PCT/US2021/044627 IPRP, Feb. 28, 2023, Micron Technology, Inc. [cited by applicant]
WO PCT/US2021/044627 Search Rep., Nov. 26, 2021, Micron Technology, Inc. [cited by applicant]
WO PCT/US2021/044627 Writt. Opin., Nov. 26, 2021, Micron Technology, Inc. [cited by applicant]