Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
1. A method of forming a three-dimensional memory device, comprising:
forming a source semiconductor layer over a substrate;
forming a line trench through the source conductive layer;
forming a etch stop semiconductor rail within the line trench;
forming a laterally alternating stack of dielectric rails and sacrificial semiconductor rails over the source conductive layer and the etch stop semiconductor rail;
forming a vertically alternating stack of insulating layers and spacer material layers over the laterally alternating stack, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory stack structures through the vertically alternating stack and the laterally alternating stack, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel;
forming a backside trench through the vertically alternating stack and the laterally alternating stack by an anisotropic etch process that employs the etch stop semiconductor rail as an etch stop structure;
forming source cavities by removing the sacrificial semiconductor rails and portions of each memory film adjacent to the sacrificial semiconductor rails; and
forming source strap rails in the source cavities and directly on sidewalls of the semiconductor channels.
2. The method of claim 1 , further comprising forming a diffusion barrier dielectric liner in the line trench, wherein the etch stop semiconductor rail is formed within the diffusion barrier dielectric liner.
3. The method of claim 1 , wherein:
the line trench extends through an entire thickness of the source semiconductor layer;
the etch stop semiconductor rail is formed by deposition and planarization of a doped semiconductor material; and
a top surface of the etch stop semiconductor rail is within a same horizontal plane as a top surface of the source semiconductor layer.
4. The method of claim 1 , wherein:
the source semiconductor layer comprises a first n-doped semiconductor material;
the source strap rails comprise a second n-doped semiconductor material; and
the etch stop semiconductor rail comprises a p-doped semiconductor material.
5. The method of claim 1 , wherein:
each of the dielectric rails and the sacrificial semiconductor rails laterally extend along a first horizontal direction;
the etch stop semiconductor rail extends along a second horizontal direction that is different from the first horizontal direction.
6. The method of claim 1 , further comprising forming an insulating wall structure within the backside trench after formation of the source strap rails.
7. The method of claim 1 , further comprising:
forming a dielectric liner over the laterally alternating stack; and
forming a cap semiconductor layer over the dielectric liner,
wherein:
the vertically alternating stack is formed over the cap semiconductor layer;
portions of the dielectric liner overlying the sacrificial semiconductor rails is removed after removal of the sacrificial semiconductor rails; and
the source strap rails are formed on a bottom surface of the cap semiconductor layer.
8. The method of claim 1 , further comprising:
forming source-level memory openings within the laterally alternating stack of the dielectric rails and the sacrificial semiconductor rails;
forming sacrificial semiconductor pedestals within the source-level memory openings; and
forming memory openings through the vertically alternating stack by etching through the vertically alternating stack and by removing the sacrificial semiconductor pedestals, wherein each of the memory openings includes a volume of a respective one of the sacrificial semiconductor pedestals,
wherein memory stack structures are formed in the memory openings.
9. The method of claim 8 , wherein:
a lower portion of each memory stack structure including a volume of a respective sacrificial semiconductor pedestal has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure that adjoins a top end of the bulging portion; and
the source strap rails contact the semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure.
10. The method of claim 1 , further comprising forming memory openings through the vertically alternating stack and the laterally alternating stack,
wherein:
surfaces of each memory opening include a sidewall of a respective sacrificial semiconductor rail and a sidewall of a respective dielectric rail; and
each memory opening has a monotonically increasing lateral extent as a function of a vertical distance from the substrate between a bottommost surface of a respective memory opening and a bottommost spacer material layer within the vertically alternating stack.