3D NAND memory device with non-uniform channel structure and method for forming the same
Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.
1. A semiconductor device, comprising:
a first die comprising:
a first stack of layers including a semiconductor layer on a back side of the first die;
a second stack of layers including gate layers and first insulating layers alternatingly stacked on a face side of the first die, the face side being opposite to the back side, the second stack of layers being stacked on the first stack of layers in a first direction from the face side to the back side; and
a vertical structure extending along the first direction through the first stack of layers and the second stack of layers, the vertical structure including a first portion and a second portion, the first portion being disposed in the first stack of layers, the second portion extending through the second stack of layers, the first portion having a different dimension than the second portion in a second direction parallel to a main surface of the first die, the second direction being perpendicular to the first direction.
2. The semiconductor device of claim 1 , wherein:
the vertical structure includes a channel structure in a core region, and
the channel structure includes a channel layer extending in the first portion and the second portion.
3. The semiconductor device of claim 2 , wherein the second portion comprises:
a tunneling layer surrounding the channel layer;
a charge trapping layer surrounding the tunneling layer; and
a barrier layer surrounding the charge trapping layer.
4. The semiconductor device of claim 2 , wherein the channel layer, in the first portion, is in contact with the semiconductor layer.
5. The semiconductor device of claim 2 , wherein:
the semiconductor layer is a source connection layer that is configured to connect the channel layer to an array common source.
6. The semiconductor device of claim 1 , wherein the first portion has a larger dimension than the second portion in the direction parallel to the main surface of the first die.
7. The semiconductor device of claim 1 , wherein a first lateral periphery of the first portion extends from a second periphery of the second portion by 10-100 nm.
8. The semiconductor device of claim 1 , further comprising:
a first conductive structure disposed on the backside of the first die, the first conductive structure conductively connected with the semiconductor layer; and
a second conductive structure disposed on the backside of the first die, the second conductive structure conductively connected with a contact structure disposed on the face side of the first die.
9. The semiconductor device of claim 1 , wherein the vertical structure includes at least one of a gate line slit (GLS) structure or a dummy channel structure.
10. The semiconductor device of claim 1 , further comprising:
memory cells on the face side of the first die; and
a second die bonded with the first die face to face, the second die including a substrate and peripheral circuitry formed on a face side of the substrate for the memory cells.
11. A memory system, comprising:
a semiconductor device, comprising:
a die including:
a first stack of layers including a semiconductor layer on a back side of the die;
a second stack of layers including gate layers and insulating layers alternatingly stacked on a face side of the die, the face side being opposite to the back side, the second stack of layers being stacked on the first stack of layers in a first direction from the face side to the back side; and
a vertical structure extending along the first direction through the first stack of layers and the second stack of layers, the vertical structure including a first portion and a second portion, the first portion being disposed in the first stack of layers, the second portion extending through the second stack of layers, the first portion having a different dimension than the second portion in a second direction parallel to a main surface of the die, the second direction being perpendicular to the first direction; and
a controller configured to control operations of the semiconductor device, the controller being connected with the semiconductor device.
12. The memory system of claim 11 , wherein:
the vertical structure includes a channel structure in a core region, and
the channel structure includes a channel layer extending in the first portion and the second portion.
13. The memory system of claim 12 , wherein the second portion comprises:
a tunneling layer surrounding the channel layer;
a charge trapping layer surrounding the tunneling layer; and
a barrier layer surrounding the charge trapping layer.
14. The memory system of claim 12 , wherein the channel layer, in the first portion, is in contact with the semiconductor layer.
15. The memory system of claim 12 , wherein:
the semiconductor layer is a source connection layer that is configured to connect the channel layer to an array common source.
16. The memory system of claim 11 , wherein the first portion has a larger dimension than the second portion in the direction parallel to the main surface of the first die.
17. The memory system of claim 11 , wherein a first lateral periphery of the first portion extends from a second periphery of the second portion by 10-100 nm.
18. The memory system of claim 11 , further comprising:
a first conductive structure disposed on the backside of the first die, the first conductive structure conductively connected with the semiconductor layer; and
a second conductive structure disposed on the backside of the first die, the second conductive structure conductively connected with a contact structure disposed on the face side of the first die.
19. The memory system of claim 11 , wherein the vertical structure includes at least one of a gate line slit (GLS) structure or a dummy channel structure.
20. The memory system of claim 11 , further comprising:
memory cells on the face side of the first die; and
a second die bonded with the first die face to face, the second die including a substrate and peripheral circuitry formed on a face side of the substrate for the memory cells.