Scan driver and display device including the same
A scan driver includes stages which sequentially output scan signals to scan signal lines during an active period of an N-th frame, and at least one of the stages includes an output node controller that supplies a gate-on voltage to a pull-up node in response to a gate control signal of a display driver, and an output controller that supplies a scan signal to a scan signal line by outputting a scan clock signal, which is input through a scan clock terminal, to the scan signal line in case that the gate-on voltage is supplied to the pull-up node, wherein the output node controller includes a thin-film transistor which is turned on in response to a simultaneous driving control signal, supplies the scan clock signal to the pull-up node, and periodically receives the scan clock signal in case that the thin-film transistor is turned off during the active period.
1. A scan driver comprising:
stages which sequentially output scan signals to scan signal lines during an active period of an N-th frame, wherein N is a positive integer, wherein
at least one of the stages comprises:
an output node controller that supplies a gate-on voltage to a pull-up node in response to a gate control signal of a display driver; and
an output controller that supplies a scan signal to a scan signal line by outputting a scan clock signal, which is input through a scan clock terminal, to the scan signal line in case that the gate-on voltage is supplied to the pull-up node, the output node controller comprising a thin-film transistor having a first electrode and a second electrode, and
the thin-film transistor is turned on in response to a simultaneous driving control signal, supplies the scan clock signal, which is input through the first electrode of the thin-film transistor, to the pull-up node to which the second electrode of the thin-film transistor is connected during a simultaneous driving period, and
the thin-film transistor periodically receives the scan clock signal through the first electrode in case that the thin-film transistor is turned off during the active period.
2. The scan driver of claim 1 , wherein the output node controller comprises:
a first transistor which is turned on in case that the pull-up node is enabled by the gate-on voltage and supplies the scan clock signal to a first capacitor connected to the first transistor in parallel;
a second transistor, which is turned on in case that a pull-down node is enabled by the gate-on voltage and supplies a gate-off voltage to the first transistor;
a third transistor turned on in case that the pull-up node is enabled by the gate-on voltage and supplies another scan clock signal to the pull-down node;
a fourth transistor which is turned on in response to a line selection signal of a sensing signal terminal or a previous carry signal and supplies the gate-on voltage to the pull-up node;
a fifth transistor which is turned on in response to the simultaneous driving control signal and supplies the scan clock signal to the pull-up node during the simultaneous driving period and periodically receives the scan clock signal through a first electrode of the fifth transistor in case that the fifth transistor is turned off in response to the simultaneous driving control signal at a level of the gate-off voltage during the active period;
a sixth transistor which electrically connects the pull-up node to another transistor or the first capacitor in response to the scan clock signal;
a seventh transistor which is turned on in case that the pull-down node is enabled and electrically connecting the sixth transistor to the first capacitor and the first transistor; and
an eighth transistor which is turned on in response to a next carry signal or another scan clock signal and supplies the gate-on voltage to the pull-down node.
3. The scan driver of claim 2 , wherein the output controller comprises:
a pull-up transistor which is turned on by the gate-on voltage of the pull-up node and that outputs the scan clock signal to a scan output terminal and the scan signal line; and
a pull-down transistor which is turned on by the gate-on voltage of the pull-down node and outputs the gate-off voltage to the scan output terminal and the scan signal line.
4. The scan driver of claim 2 , wherein the output node controller further comprises a ninth transistor which disables the pull-up node using the gate-off voltage or the scan clock signal in response to a next carry signal from a next stage.
5. The scan driver of claim 4 , wherein
at least one of the second, seventh and eighth transistors indirectly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a first active layer comprising a first oxide semiconductor material, and
at least one of the first, third, fourth, fifth and ninth transistors directly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a second active layer material comprising a second oxide semiconductor material different from the first oxide semiconductor material of the first active layer.
6. The scan driver of claim 2 , wherein
the first transistor has a gate electrode connected to the pull-up node, a first electrode connected to a second scan clock terminal and a second electrode connected to a previous carry terminal and a first electrode of the second transistor,
the second transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the first transistor and the previous carry terminal and a second electrode connected to a gate-off voltage supply terminal,
the third transistor has a gate electrode connected to the pull-up node, a first electrode connected to a first scan clock terminal and a second electrode connected to the pull-down node,
the fourth transistor has a gate electrode connected to the sensing signal terminal or the previous carry terminal, a first electrode connected to a gate-on voltage supply terminal and a second electrode connected to the pull-up node,
the fifth transistor has a gate electrode connected to a simultaneous driving control terminal to which the simultaneous driving control signal is input, a second electrode connected to the pull-up node and a second electrode connected to the scan clock terminal,
the sixth transistor has a gate electrode connected to the second scan clock terminal, a first electrode connected to the pull-up node and a second electrode connected to the second electrode of the first transistor or a first electrode of the seventh transistor,
the seventh transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the sixth transistor and a second electrode connected to the second electrode of the first transistor and the first capacitor, and
the eighth transistor has a gate electrode connected to the first scan clock terminal, a first electrode connected to the gate-on voltage supply terminal and a second electrode connected to the pull-down node.
7. The scan driver of claim 6 , wherein the output controller comprises:
a pull-up transistor having a first electrode connected to the second scan clock terminal, a gate electrode connected to the pull-up node, and a second electrode connected to a scan output terminal; and
a pull-down transistor having a first electrode connected to the scan output terminal, a gate electrode connected to the pull-down node, and a second electrode receiving the simultaneous driving control signal at a same level as the gate-off voltage during the active period.
8. The scan driver of claim 7 , wherein
the pull-down transistor comprises a first active layer comprising a first oxide semiconductor material, and
the pull-up transistor comprises a second active layer comprising a second oxide semiconductor material different from the first oxide semiconductor material of the first active layer.
9. The scan driver of claim 7 , wherein the output node controller further comprises a ninth transistor including:
a gate electrode connected to a next carry terminal,
a first electrode connected to the previous carry terminal or the gate-off voltage supply terminal, and
a second electrode connected to the pull-up node.
10. The scan driver of claim 9 , wherein
at least one of the second, seventh and eighth transistors indirectly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a first active layer comprising a first oxide semiconductor material, and
at least one of the first, third, fourth, fifth and ninth transistors directly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a second active layer comprising a second oxide semiconductor material different from the first oxide semiconductor material of the first active layer.
11. The scan driver of claim 10 , wherein
the first active layer comprises indium-gallium-zinc-oxide, and
the second active layer comprises indium-gallium-zinc-tin oxide.
12. A display device comprising:
a plurality of pixels arranged in a display area of a display panel;
a touch sensing unit disposed on a front of the display panel and integral with the display panel;
a touch driver that senses a touch of a human body or a touch pen using a plurality of touch electrodes arranged in the touch sensing unit;
a display driver that controls data voltages supplied to the plurality of pixels and image display timing of the plurality of pixels; and
a scan driver that sequentially drives scan signal lines, which are connected to the plurality of pixels, in response to a gate control signal from the display driver, wherein
the scan driver comprises stages which sequentially output scan signals to the scan signal lines during an active period of an N-th frame, wherein N is a positive integer, and at least one of the stages comprises:
an output node controller that supplies a gate-on voltage to a pull-up node in response to a gate control signal of the display driver; and
an output controller that supplies a scan signal to a scan signal line by outputting a scan clock signal, which is input through a scan clock terminal, to the scan signal line in case that the gate-on voltage is supplied to the pull-up node, the output node controller comprising a thin-film transistor having a first electrode and a second electrode, and
the thin-film transistor is turned on in response to a simultaneous driving control signal, supplies the scan clock signal, which is input through the first electrode of the thin-film transistor, to the pull-up node to which the second electrode of the thin-film transistor is connected during a simultaneous driving period, and
the thin-film transistor periodically receives the scan clock signal through the first electrode in case that the thin-film transistor is turned off during the active period.
13. The display device of claim 12 , wherein the output node controller comprises:
a first transistor which is turned on in case that the pull-up node is enabled by the gate-on voltage and supplies the scan clock signal to a first capacitor connected to the first transistor in parallel;
a second transistor which is turned on in case that a pull-down node is enabled by the gate-on voltage and supplies a gate-off voltage to the first transistor;
a third transistor which is turned on in case that the pull-up node is enabled by the gate-on voltage and supplies another scan clock signal to the pull-down node;
a fourth transistor which is turned on in response to a line selection signal of a sensing signal terminal or a previous carry signal and supplies the gate-on voltage to the pull-up node;
a fifth transistor which is turned on in response to the simultaneous driving control signal and supplies the scan clock signal to the pull-up node during the simultaneous driving period and periodically receiving the scan clock signal through a first electrode of the fifth transistor in case that the fifth transistor is turned off in response to the simultaneous driving control signal at a level of the gate-off voltage during the active period;
a sixth transistor which electrically connects the pull-up node to another transistor or the first capacitor in response to the scan clock signal;
a seventh transistor which is turned on in case that the pull-down node is enabled and electrically connecting the sixth transistor to the first capacitor and the first transistor; and
an eighth transistor which is turned on in response to a next carry signal or another scan clock signal and supplies the gate-on voltage to the pull-down node.
14. The display device of claim 13 , wherein the output node controller further comprises a ninth transistor which disables the pull-up node using the gate-off voltage or the scan clock signal in response to a next carry signal from a next stage.
15. The display device of claim 13 , wherein
the first transistor has a gate electrode connected to the pull-up node, a first electrode connected to a second scan clock terminal and a second electrode connected to a previous carry terminal and a first electrode of the second transistor,
the second transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the first transistor and the previous carry terminal and a second electrode connected to a gate-off voltage supply terminal,
the third transistor has a gate electrode connected to the pull-up node, a first electrode connected to a first scan clock terminal and a second electrode connected to the pull-down node,
the fourth transistor has a gate electrode connected to the sensing signal terminal or the previous carry terminal, a first electrode connected to a gate-on voltage supply terminal and a second electrode connected to the pull-up node,
the fifth transistor has a gate electrode connected to a simultaneous driving control terminal to which the simultaneous driving control signal is input, a second electrode connected to the pull-up node and a second electrode connected to the scan clock terminal,
the sixth transistor has a gate electrode connected to the second scan clock terminal, a first electrode connected to the pull-up node and a second electrode connected to the second electrode of the first transistor or a first electrode of the seventh transistor,
the seventh transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the sixth transistor and a second electrode connected to the second electrode of the first transistor and the first capacitor, and
the eighth transistor has a gate electrode connected to the first scan clock terminal, a first electrode connected to the gate-on voltage supply terminal and a second electrode connected to the pull-down node.
16. The display device of claim 15 , wherein the output controller comprises:
a pull-up transistor having a first electrode connected to the second scan clock terminal, a gate electrode connected to the pull-up node, and a second electrode connected to a scan output terminal; and
a pull-down transistor having a first electrode connected to the scan output terminal, a gate electrode connected to the pull-down node, and a second electrode connected to the simultaneous driving control terminal.
17. The display device of claim 15 , wherein the output node controller further comprises a ninth transistor having a gate electrode connected to a next carry terminal, a first electrode connected to the previous carry terminal or the gate-off voltage supply terminal, and a second electrode connected to the pull-up node.
18. The display device of claim 17 , wherein
at least one of the second, seventh and eighth transistors indirectly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a first active layer comprising a first oxide semiconductor material, and
at least one of the first, third, fourth, fifth and ninth transistors directly connected to the pull-up node among the first through ninth transistors included in the output node controller comprises a second active layer comprising a second oxide semiconductor material different from the first oxide semiconductor material of the first active layer.