Method of forming semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.
1. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming a target layer on the substrate;
forming a hard mask layer on the target layer; and
implanting a group IV-A element into the hard mask layer to increase a number of sp2 orbital bonds in the hard mask layer, wherein a number of sp3 orbital bonds is greater than a number of sp2 orbital bonds of the group IV-A element doped in the hard mask layer.
2. The method for forming the semiconductor structure of claim 1 , wherein after implanting the hard mask layer with the group IV-A element, a ratio of a number of sp3 orbital bonds to a number of sp2 orbital bonds in the hard mask layer is 2.5-4.0.
3. The method for forming the semiconductor structure of claim 1 , wherein the hard mask layer comprises a diamond-like carbon (DLC) layer, and the group IV-A element is carbon.
4. The method for forming the semiconductor structure of claim 1 , wherein implanting the hard mask layer with the group IV-A element is performed by an ex-situ implantation method.
5. The method for forming the semiconductor structure of claim 1 , after implanting the hard mask layer with the group IV-A element, further comprising:
patterning the hard mask layer to expose the target layer;
forming a plurality of spacers on sidewalls of the patterned hard mask layer; and
removing the hard mask layer.
6. The method for forming the semiconductor structure of claim 5 , wherein patterning the hard mask layer to expose the target layer comprises an anisotropic etching process.
7. The method for forming the semiconductor structure of claim 6 , wherein the anisotropic etching process etches the hard mask layer with an aspect ratio in the range of 1:1 to 1:200.
8. The method for forming the semiconductor structure of claim 1 , further comprising:
using the hard mask layer to pattern the target layer to form a gate stack, wherein the gate stack comprises a floating gate layer, a control gate layer over the floating gate layer, and an inter-gate dielectric layer between the floating gate layer and the control gate layer.
9. The method for forming the semiconductor structure of claim 1 , further comprising:
using the hard mask layer to pattern the target layer to form openings exposing the substrate;
removing the hard mask layer; and
forming a plurality of conductive contacts in the openings.
10. The method for forming the semiconductor structure of claim 1 , wherein a compressive stress of the hard mask layer doped with the group IV-A element is −100 MPa to 100 MPa.
11. The method for forming the semiconductor structure of claim 1 , wherein the hard mask layer comprises one or more layers of a group of SiGe, GeC, and SiC.
12. The method for forming the semiconductor structure of claim 1 , wherein a doping concentration of the group IV-A element is 10 10 cm −3 to 10 20 cm −3 .
13. The method for forming the semiconductor structure of claim 1 , a compressive stress of the hard mask layer after implanting the group IV-A element is less than an absolute value of 10% of a compressive stress of the hard mask layer before implanting the group IV-A element.
14. The method for forming the semiconductor structure of claim 1 , an etching resistance of the hard mask layer after implanting the group IV-A element is at least 85% of an etching resistance of the hard mask layer before implanting the group IV-A element.
15. The method for forming the semiconductor structure of claim 1 , a thickness of the hard mask layer is in a range of 1 nm to 1 μm.
16. The method for forming the semiconductor structure of claim 1 , an implantation energy of the group IV-A element is in a range of 100 eV to 10 MeV.