Integrated circuit devices including a vertical field-effect transistor and methods of forming the same
Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.
1. A method of forming an integrated circuit device, the method comprising:
forming channel regions that comprise first, second, and third channel regions on a substrate, wherein the first, second, and third channel regions each protrudes from the substrate in a first direction and are sequentially arranged in a second direction, wherein the first direction is perpendicular to an upper surface of the substrate, and the second direction is parallel with the upper surface of the substrate;
forming first and second bottom source/drain regions in the substrate, wherein the first bottom source/drain region is between the first and second channel regions in a plan view, and the second bottom source/drain region is between the second and third channel regions in the plan view;
forming first and second isolation layers in the substrate, wherein a portion of the first isolation layer is in the first bottom source/drain region, and a portion of the second isolation layer is in the second bottom source/drain region; and then
forming top source/drain regions on the channel regions,
wherein forming the top source/drain regions comprises a first process that forms the top source/drain regions on the first and third channel regions and a second process that suppresses a formation of the top source/drain regions on the second channel region,
wherein upper surfaces of the first, second, and third channel regions are coplanar with each other in the first direction, and
wherein at least a portion of the second channel region does not overlap the top source/drain regions in the first direction.
2. The method of claim 1 , wherein forming the first and second isolation layers comprises:
forming a first trench in the substrate by removing a portion of the first bottom source/drain region and a second trench in the substrate by removing a portion of the second bottom source/drain region; and
forming the first and second isolation layers in the first and the second trenches, respectively.
3. The method of claim 2 , further comprising:
forming a liner layer conformally on the second channel region;
forming a mask layer on the liner layer, wherein the mask layer comprises a first portion overlapping the portion of the first bottom source/drain region and a second portion overlapping the portion of the second bottom source/drain region; and
removing the first portion of the mask layer and the second portion of the mask layer, where removing the first and second portions of the mask layer exposes the liner layer.
4. The method of claim 1 , wherein the second process comprises forming an inhibition layer contacting the upper surface of the second channel region after the forming channel regions and before the first process, and
wherein the first process comprises growing the top source/drain regions using an epitaxial growth process.
5. A method of forming an integrated circuit device, the method comprising:
forming channel regions that comprise first, second, and third channel regions on a substrate, wherein the first, second, and third channel regions each protrudes from the substrate in a vertical direction and are sequentially arranged in a horizontal direction;
forming first, second, third, and fourth bottom source/drain regions in the substrate, wherein the first bottom source/drain region is between the first and second channel regions in the horizontal direction, the second bottom source/drain region is between the second and third channel regions in the horizontal direction, the third bottom source/drain region is opposite to the first bottom source/drain region with respect to the first channel region in the horizontal direction, and the fourth bottom source/drain region is opposite to the second bottom source/drain region with respect to the third channel region in the horizontal direction;
forming first and second isolation layers in the substrate, wherein a portion of the first isolation layer is in the first bottom source/drain region, and a portion of the second isolation layer is in the second bottom source/drain region; and then
forming top source/drain regions on the channel regions,
wherein forming the top source/drain regions comprises forming a first top source/drain region on the first channel region and forming a third top source/drain region on the third channel region, and
wherein, responsive to forming the top source/drain regions, the second channel region is free of the top source/drain regions thereon.
6. The method of claim 5 , wherein the second channel region is a dummy channel region.
7. The method of claim 6 , wherein the first top source/drain region and the third top source/drain region have a substantially equal volume.