IP Library Granted Patent US 12,379,543
Granted Patent B2
US 12,379,543 · App. 18/651,273 · Granted Aug 5, 2025

Photonic integrated circuit system and method of fabrication

Inventors: Lei Wang (Santa Clara, CA); Thomas W. Baehr-Jones (Santa Clara, CA); Mitchell A. Nahmias (Santa Clara, CA)
Assignee: Luminous Computing, Inc.
G02B6/12019G02B6/132G02B6/136G02B2006/12061
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Quick Facts
Patent No.
US 12,379,543
App. No.
18/651,273
Granted
Aug 5, 2025
Kind
B2
Abstract

A photonic integrated circuit (PIC) system, preferably including a substrate, one or more photonic connections, and a plurality of circuit blocks. The circuit blocks preferably include one or more waveguides that are optically coupled to the photonic connections, such as by transition features. A method of PIC fabrication, preferably including defining a PIC structure and defining circuit blocks. The circuit blocks are preferably defined onto one or more template regions defined by the PIC structure. Photonic connections are preferably defined as part of the PIC structure. Transition features, such as transitions between the photonic connections and the circuit blocks, are preferably defined concurrently with defining the circuit blocks.

Claims (25)

1. A method of fabricating a photonic integrated circuit (PIC) on a substrate, comprising:

lithographically defining a transition between a first photonic circuit block and a first connecting waveguide having a first width using a first lithographic patterning technique, the photonic integrated circuit comprising:

a transition waveguide having a second width, configured for optically coupling to a photonic element in the first photonic circuit block; and

a transition feature extending between the transition waveguide and the first connecting waveguide, tapering from the first width to the second width;

wherein defining the transition feature and the transition waveguide comprises providing a tapered masked feature over the first connecting waveguide and the first photonic circuit block configured to define the transition feature and the transition waveguide; and

wherein the tapered masked feature has a maximum width greater than the first width, and extends past the first width in both directions.

2. The method according to claim 1 , further comprising lithographically defining a PIC structure on the substrate using a second lithographic patterning technique, the PIC structure comprising:

a plurality of photonic circuit blocks including the first photonic circuit block; and

a set of connecting waveguides, including the first connecting waveguide, each connecting waveguide of the set of connecting waveguides having the first width, and optically coupling respective circuit blocks of the plurality of photonic circuit blocks.

3. The method of claim 2 , wherein each photonic circuit block is substantially identical.

4. Then method of claim 2 , wherein the first lithographic patterning technique is different than the second lithographic patterning technique.

5. The method of claim 4 , wherein the first lithographic patterning technique is selected from a group comprising: stepper photolithography, electron beam lithography, and holographic lithography.

6. The method of claim 5 , wherein the second lithographic patterning technique comprises a contact lithography technique, a nanoimprint lithography technique or a direct write lithography technique.

7. The method of claim 2 , wherein: the PIC structure is defined within a layer on the substrate; and for each photonic circuit block of the plurality of photonic circuit blocks is defined within the layer.

8. The method of claim 7 , wherein the substrate is a silicon-on-insulator substrate, and wherein the layer is a silicon layer.

9. The method of claim 2 , wherein each of the plurality of photonic circuit blocks includes an electro-optical transducer.

10. The method according to claim 1 , wherein the tapered masked feature extends past the first width in each direction by an amount greater than 10 nm.

11. The method according to claim 1 , wherein the tapered masked feature extends past the first width in each direction by an amount greater than 30 nm.

12. The method according to claim 1 , wherein the transition feature has a linear profile.

13. The method according to claim 1 , wherein the transition feature has a curved profile.

14. The method according to claim 1 , wherein the transition feature has a quadratic profile.

15. The method according to claim 1 , wherein the transition feature defines an adiabatic taper.

16. The method according to claim 1 , wherein the transition waveguide is not substantially collinear with the connecting waveguide.

17. The method of claim 1 , wherein the connecting waveguide is a multi-mode waveguide; and the transition waveguide is a single-mode waveguide.

18. The method of claim 1 , wherein the first photonic circuit block includes an electro-optical transducer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2026
From: LUMINOUS COMPUTING, INC.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 073930/0688 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2025
From: WANG, LEI; BAEHR-JONES, THOMAS W.; NAHMIAS, MITCHELL A.
To: LUMINOUS COMPUTING INC.
Reel/Frame 071689/0119 →
Continuity (5)
Continuation 18176861 · Mar 1, 2023
Continuation 17671049 · Feb 14, 2022
Provisional Application 63281567 · Nov 19, 2021
Provisional Application 63152275 · Feb 22, 2021
Related Publication 20240280748A1 · Aug 22, 2024
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