IP Library › Granted Patent US 12,381,547
Granted Patent B2
US 12,381,547 · App. 18/285,547 · Granted Aug 5, 2025

Layout of gate driver circuit for high-speed switching devices

Inventors: Shohei Masuda (Markham, CA); Ahmad Yafaoui (Markham, CA); Andrew Dickson (Markham, CA)
Assignee: MURATA MANUFACTURING CO., LTD.
H03K17/04206H03K17/0424H03K2217/0081
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,381,547
App. No.
18/285,547
Granted
Aug 5, 2025
Kind
B2
Abstract

A switching circuit includes a first switch; a second switch connected in series with the first switch; a first isolated driver connected to a gate terminal of the first switch; a second isolated driver connected to a gate terminal of the second switch; and a transformer including a primary winding connected to an auxiliary power supply, a first secondary winding to supply a first voltage to the first isolated driver, and a second secondary winding to supply a second voltage to the second isolated driver.

Claims (54)

1. A switching circuit comprising:

a first switch;

a second switch connected in series with the first switch;

a first isolated driver connected to a gate terminal of the first switch;

a second isolated driver connected to a gate terminal of the second switch; and

a transformer including a primary winding connected to an auxiliary power supply, a first secondary winding to supply a first voltage to the first isolated driver, and a second secondary winding to supply a second voltage to the second isolated driver; wherein

a length of at least one of a first gate line connected between the first isolated driver and the gate terminal of the first switch and a second gate line connected between the second isolated driver and the gate terminal of the second switch is equal to or shorter than a width of at least one of the first switch and the second switch.

2. The switching circuit according to claim 1 , further comprising:

a first rectifier connected between the first secondary winding and the first isolated driver; and

a second rectifier connected between the second secondary winding and the second isolated driver.

3. The switching circuit according to claim 1 , wherein each of the first switch and the second switch is a GaN transistor.

4. The switching circuit according to claim 1 , wherein a source terminal of the first switch is connected to a drain terminal of the second switch.

5. The switching circuit according to claim 1 , further comprising a control circuit connected to each of the first isolated driver and the second isolated driver.

6. The switching circuit according to claim 1 , wherein an output of the transformer to the first isolated driver is located on a different side of the transformer from an output of the transformer to the second isolated driver.

7. The switching circuit according to claim 1 , wherein a size of the transformer is smaller than a size of either of the first isolated driver or the second isolated driver.

8. The switching circuit according to claim 1 , wherein each of the first switch, the second switch, the first isolated driver, the second isolated driver, and the transformer is provided on a single circuit board or a single substrate.

9. A switching circuit comprising:

a first switch;

a second switch connected in series with the first switch;

a first isolated driver connected to a gate terminal of the first switch;

a second isolated driver connected to a gate terminal of the second switch; and

a transformer including a primary winding connected to an auxiliary power supply, a first secondary winding to supply a first voltage to the first isolated driver, and a second secondary winding to supply a second voltage to the second isolated driver; wherein

a first gate-line current loop of the first switch is defined by a path from the first isolated driver to the gate terminal of the first switch and to a ground terminal of the first isolated driver;

a second gate-line current loop of the second switch is defined by a path from the second isolated driver to the gate terminal of the second switch and to a ground terminal of the second isolated driver; and

a length of at least one of the first gate-line current loop and the second gate-line current loop is equal to or shorter than a width of at least one of the first switch and the second switch.

10. A gate driver device comprising:

a substrate including terminals to receive an auxiliary voltage from an auxiliary power supply that is not located on the substrate;

a first switch and a second switch that are located on the substrate and that are connected in series;

a first isolated driver that is located on the substrate, that is connected to the first switch, and that includes first input circuitry and first output circuitry that are isolated from each other;

a second isolated driver that is located on the substrate, that is connected to the second switch, and that includes second input circuitry and second output circuitry that are isolated from each other;

a transformer that is located on the substrate and that includes:

a primary winding to receive the auxiliary voltage;

a first secondary winding to supply a first voltage to the first output circuitry; and

a second secondary winding to supply a second voltage to the second output circuitry.

11. The gate driver device according to claim 10 , further comprising:

a first rectifier connected between the first secondary winding and the first isolated driver; and

a second rectifier connected between the second secondary winding and the second isolated driver.

12. The gate driver device according to claim 10 , wherein each of the first switch and the second switch is a GaN transistor.

13. The gate driver device according to claim 10 , wherein a source terminal of the first switch is connected to a drain terminal of the second switch.

14. The gate driver device according to claim 10 , wherein a first line connecting the transformer to the first isolated driver is located on a different side of the transformer from a second line connecting the transformer to the second isolated driver.

15. The gate driver device according to claim 10 , wherein a size of the transformer is smaller than a size of either of the first isolated driver or the second isolated driver.

16. The gate driver device according to claim 10 , wherein

the first isolated driver and the second isolated driver are located on a first side of the substrate; and

the first switch, the second switch, and the transformer are located on a second side of the substrate opposite to the first side.

17. The gate driver device according to claim 10 , wherein a length of at least one of a first gate line connected between the first isolated driver and a gate terminal of the first switch and a second gate line connected between the second isolated driver and a gate terminal of the second switch is equal to or shorter than a width of at least one of the first switch and the second switch.

18. The gate driver device according to claim 10 , wherein:

a first gate-line current loop of the first switch is defined by a path from the first isolated drivers to a gate terminal of the first switch and to a ground terminal of the first isolated driver;

a second gate-line current loop of the second switch is defined by a path from the second isolated driver to the gate terminal of the second switch and to a ground terminal of the second isolated driver; and

a length of at least one of the first gate-line current loop and the second gate-line current loop is equal to or shorter than a width of at least one of the first switch and the second switch.

19. A gate driver system comprising:

the gate driver device of claim 10 ; and

the auxiliary power supply that is not located on the substrate.

20. The gate driver system according to claim 19 , further comprising a control circuit connected to each of the first isolated driver and the second isolated driver.

21. The gate driver system of claim 19 , wherein the auxiliary power supply is a pulse voltage power supply.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE DOCKET NUMBER TO CORRECTLY READ AS "36857. 386.US PREVIOUSLY RECORDED AT REEL: 065209 FRAME: 0378. ASSIGNOR(S) HEREBY CONFIRMS THE ENTIRE INTEREST. Recorded Oct 20, 2023
From: MASUDA, SHOHEI; YAFOUI, AHMAD; DICKSON, ANDREW
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 065300/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2023
From: MASUDA, SHOHEI; YAFOUI, AHMAD; DICKSON, ANDREW
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 065209/0378 →
Continuity (2)
Provisional Application 63175239 · Apr 15, 2021
Related Publication 20240178828A1 · May 30, 2024
References Cited (10)
US 7965522B1 · Hornberger · 2011 [cited by examiner]
US 10431424B2 · Mavretic et al. · 2019 [cited by applicant]
US 20120133420A1 · Draxelmayr et al. · 2012 [cited by applicant]
US 20150381065A1 · Yonezawa et al. · 2015 [cited by applicant]
US 20180109173A1 · Nishijima · 2018 [cited by applicant]
US 20200076415A1 · Lee · 2020 [cited by examiner]
CN 111884492A · 2020 [cited by applicant]
WO 2018148218A1 · 2018 [cited by applicant]
Half-bridge power device gate driver circuit with isolation using integrated magnetic component and carrier signal phase switching, IEEE Xplore, Sep. 15, 2011 (Year: 2011). [cited by examiner]
Official Communication issued in International Patent Application No. PCT/US2022/024811, mailed on Aug. 1, 2022. [cited by applicant]