IP Library Granted Patent US 12,381,806
Granted Patent B2
US 12,381,806 · App. 18/386,245 · Granted Aug 5, 2025

Methods, systems, and computer readable media for testing ingress timestamping using lane skewing

Inventor: Pinaki Chakrabarti (League City, TX)
Assignee: KEYSIGHT TECHNOLOGIES, INC.
H04L43/50H04L43/106
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,381,806
App. No.
18/386,245
Granted
Aug 5, 2025
Kind
B2
Abstract

One example method occurs at a test system implemented using at least one processor. The method includes receiving test configuration information associated with a test session for causing one or more packets to be transmitted via lanes connecting a transmitter and a receiver in a test environment; transmitting, from the transmitter and to the receiver, a first packet of the test session, wherein transmitting the first packet as data blocks and sending the data blocks via the lanes, wherein transmitting the first packet includes emulating lane skewing associated with one or more of the lanes causing at least some of the data blocks to arrive at different times; receiving a first ingress timestamp associated with the first packet; and analyzing the first ingress timestamp and a first expected ingress timestamp based on lane skew information associated with the test session.

Claims (58)

1. A method for testing ingress timestamping using lane skewing, the method comprising:

at a test system implemented using at least one processor:

receiving test configuration information associated with a test session for causing one or more packets to be transmitted via lanes connecting a transmitter and a receiver in a test environment;

transmitting, from the transmitter and to the receiver, a first packet of the test session, wherein transmitting the first packet includes segmenting the first packet into a first plurality of data blocks and sending the first plurality of data blocks via the lanes, wherein transmitting the first packet includes emulating lane skewing associated with one or more of the lanes causing at least some of the first plurality of data blocks to arrive at the receiver at different times due to different amounts of emulated lane skew;

receiving a first ingress timestamp associated with the first packet;

determining, based on the emulated lane skew, a first expected ingress timestamp for the first packet;

analyzing the first ingress timestamp and the first expected ingress timestamp to determine whether the first ingress timestamp matches the first expected ingress timestamp;

generating a first test result associated with the first ingress timestamp;

during the test session and prior to transmitting a second packet of the test session:

modifying the test environment including modifying an emulated lane skewing configuration for one or more of the lanes such that a different lane of the lanes has the least buffer delay of the lanes than when the first packet was transmitted;

transmitting, from the transmitter and to the receiver, the second packet of the test session, wherein transmitting the second packet includes segmenting the second packet into a second plurality of data blocks and sending the second plurality of data blocks via the lanes, wherein transmitting the second packet includes emulating lane skewing using the modified emulated lane skewing configuration and causing at least some of the second plurality of data blocks to arrive at the receiver at different times;

receiving a second ingress timestamp associated with the second packet:

analyzing the second ingress timestamp and a second expected ingress timestamp based on updated lane skew information associated with the test session; and

generating a second test result associated with the second ingress timestamp.

2. The method of claim 1 wherein each of the lanes includes a physical coding sublayer (PCS) lane, a serial channel, or a physical channel.

3. The method of claim 1 wherein the lane skew information indicates that a first lane of the lanes has the least buffer delay of the lanes and that a first data block comprising a first start of frame delimiter of the first packet traverses a second lane of the lanes.

4. The method of claim 1 wherein the first test result indicates whether the first ingress timestamp is generated using timing information associated with the lane having the least buffer delay of the lanes regardless of which lane of the lanes a first data block comprising a first start of frame delimiter of the first packet traverses.

5. The method of claim 1 wherein the test configuration information includes lane skewing configuration information for emulating lane skewing during the test session.

6. The method of claim 1 wherein modifying the emulated lane skewing configuration includes modifying the emulated lane skewing configuration to cause a second data block comprising a second start of frame delimiter for the second packet to traverse a different lane than a first data block comprising a first start of frame delimiter for the first packet.

7. The method of claim 1 wherein the lane skew information indicates that a second lane of the lanes has the least buffer delay of the lanes and that a second data block comprising a second start of frame delimiter of the second packet traverses a first lane of the lanes.

8. The method of claim 1 wherein the second test result indicates whether the second ingress timestamp is generated using timing information associated with the lane having the least buffer delay of the lanes regardless of which lane of the lanes a second data block comprising a second start of frame delimiter of the second packet traverses.

9. A test system for testing ingress timestamping using lane skewing, the system comprising:

a memory; and

at least one processor,

wherein the test system is configured for:

receiving test configuration information associated with a test session for causing one or more packets to be transmitted via lanes connecting a transmitter and a receiver in a test environment;

transmitting, from the transmitter and to the receiver, a first packet of the test session, wherein transmitting the first packet includes segmenting the first packet into a first plurality of data blocks and sending the first plurality of data blocks via the lanes, wherein transmitting the first packet includes emulating lane skewing associated with one or more of the lanes causing at least some of the first plurality of data blocks to arrive at the receiver at different times due to different amounts of emulated lane skew;

receiving a first ingress timestamp associated with the first packet;

determining, based on the emulated lane skew, a first expected ingress timestamp for the first packet;

analyzing the first ingress timestamp and the first expected ingress timestamp to determine whether the first ingress timestamp matches the first expected ingress timestamp;

generating a first test result associated with the first ingress timestamp;

during the test session and prior to transmitting a second packet of the test session:

modifying the test environment including modifying an emulated lane skewing configuration for one or more of the lanes such that a different lane of the lanes has the least buffer delay of the lanes than when the first packet was transmitted;

transmitting, from the transmitter and to the receiver, the second packet of the test session, wherein transmitting the second packet includes segmenting the second packet into a second plurality of data blocks and sending the second plurality of data blocks via the lanes, wherein transmitting the second packet includes emulating lane skewing using the modified emulated lane skewing configuration and causing at least some of the second plurality of data blocks to arrive at the receiver at different times;

receiving a second ingress timestamp associated with the second packet;

analyzing the second ingress timestamp and a second expected ingress timestamp based on updated lane skew information associated with the test session; and

generating a second test result associated with the second ingress timestamp.

10. The test system of claim 9 wherein each of the lanes includes a physical coding sublayer (PCS) lane, a serial channel, or a physical channel.

11. The test system of claim 9 wherein the lane skew information indicates that a first lane of the lanes has the least buffer delay of the lanes and that a first data block comprising a first start of frame delimiter of the first packet traverses a second lane of the lanes.

12. The test system of claim 9 wherein the first test result indicates whether the first ingress timestamp is generated using timing information associated with the lane having the least buffer delay of the lanes regardless of which lane of the lanes a first data block comprising a first start of frame delimiter of the first packet traverses.

13. The test system of claim 9 wherein the test configuration information includes lane skewing configuration information for emulating lane skewing during the test session.

14. The test system of claim 9 wherein the test system performs a transmit qualification test for determining transmit port delay and/or physical media delay prior to executing the test session.

15. The test system of claim 9 wherein the test system is configured for modifying the emulated lane skewing configuration to cause a second data block comprising a second start of frame delimiter for the second packet to traverse a different lane than a first data block comprising a first start of frame delimiter for the first packet.

16. The test system of claim 9 wherein the lane skew information indicates that a second lane of the lanes has the least buffer delay of the lanes and that a second data block comprising a second start of frame delimiter of the second packet traverses a first lane of the lanes.

17. The test system of claim 9 wherein the second test result indicates whether the second ingress timestamp is generated using timing information associated with the lane having the least buffer delay of the lanes regardless of which lane of the lanes a second data block comprising a second start of frame delimiter of the second packet traverses.

18. A non-transitory computer readable medium comprising computer executable instructions embodied in the non-transitory computer readable medium that when executed by at least one processor of a test system perform steps comprising:

receiving test configuration information associated with a test session for causing one or more packets to be transmitted via lanes connecting a transmitter and a receiver in a test environment;

transmitting, from the transmitter and to the receiver, a first packet of the test session, wherein transmitting the first packet includes segmenting the first packet into a first plurality of data blocks and sending the first plurality of data blocks via the lanes, wherein transmitting the first packet includes emulating lane skewing associated with one or more of the lanes causing at least some of the first plurality of data blocks to arrive at the receiver at different times due to different amounts of emulated lane skew;

receiving a first ingress timestamp associated with the first packet;

determining, based on the emulated lane skew, a first expected ingress timestamp for the first packet;

analyzing the first ingress timestamp and the first expected ingress timestamp to determine whether the first ingress timestamp matches the first expected ingress timestamp;

generating a first test result associated with the first ingress timestamp;

during the test session and prior to transmitting a second packet of the test session:

modifying the test environment including modifying an emulated lane skewing configuration for one or more of the lanes such that a different lane of the lanes has the least buffer delay of the lanes than when the first packet was transmitted;

transmitting, from the transmitter and to the receiver, the second packet of the test session, wherein transmitting the second packet includes segmenting the second packet into a second plurality of data blocks and sending the second plurality of data blocks via the lanes, wherein transmitting the second packet includes emulating lane skewing using the modified emulated lane skewing configuration and causing at least some of the second plurality of data blocks to arrive at the receiver at different times;

receiving a second ingress timestamp associated with the second packet;

analyzing the second ingress timestamp and a second expected ingress timestamp based on updated lane skew information associated with the test session; and

generating a second test result associated with the second ingress timestamp.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2023
From: CHAKRABARTI, PINAKI
To: KEYSIGHT TECHNOLOGIES, INC.
Reel/Frame 065483/0063 →
Continuity (2)
Provisional Application 63536537 · Sep 5, 2023
Related Publication 20250080447A1 · Mar 6, 2025
References Cited (42)
US 6031847A · Collins et al. · 2000 [cited by applicant]
US 6999891B2 · Pepper · 2006 [cited by applicant]
US 9094307B1 · Edsall et al. · 2015 [cited by applicant]
US 9118566B1 · Mendel · 2015 [cited by examiner]
US 9337934B1 · Agazzi et al. · 2016 [cited by applicant]
US 9935707B2 · Pepper et al. · 2018 [cited by applicant]
US 10313100B2 · Yim · 2019 [cited by applicant]
US 10554455B2 · Schnizler · 2020 [cited by applicant]
US 11265096B2 · Bordogna et al. · 2022 [cited by applicant]
US 11552871B2 · Sela et al. · 2023 [cited by applicant]
US 11606157B1 · Wasko et al. · 2023 [cited by applicant]
US 11652561B2 · Leong et al. · 2023 [cited by applicant]
US 20040177291A1 · Goyal et al. · 2004 [cited by applicant]
US 20050144342A1 · Renaud et al. · 2005 [cited by applicant]
US 20060074622A1 · Scott · 2006 [cited by examiner]
US 20070088991A1 · Shin et al. · 2007 [cited by applicant]
US 20140269769A1 · Gresham · 2014 [cited by examiner]
US 20150071642A1 · Tanaka et al. · 2015 [cited by applicant]
US 20170099101A1 · Pepper et al. · 2017 [cited by applicant]
US 20190044637A1 · Gulstone · 2019 [cited by examiner]
US 20190356897A1 · Karivaradaswamy · 2019 [cited by examiner]
US 20210152271A1 · Bordogna · 2021 [cited by examiner]
US 20220408382A1 · Mysore · 2022 [cited by examiner]
US 20240267317A1 · Ameling · 2024 [cited by examiner]
JP 2011103595A · 2011 [cited by examiner]
Tim Warland, “Understanding Skew in 100GBASE-R4 applications”, EE Times, pp. 1-7 (2011). [cited by applicant]
IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems Local and Metropolitan Area Networks—Specific Requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Phys… [cited by applicant]
“IEEE Standard for Ethernet,” IEEE Computer Society, LAN/MAN Standards Committee, pp. 1-7025, IEEE Std 802.3™-2022. [cited by applicant]
“IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems,” IEEE Instrumentation and Measurement Society, pp. 1-499, IEEE Std 1588™M-2019. [cited by applicant]
Calnex Solutions Ltd., “Implementing IEEE 1588v2 for use in the mobile backhaul,” Technical Brief, pp. 1-24, 2009. [cited by applicant]
Chandra Mallela et al., “Timing models for PTP in Ethernet networks,” IEEE Instrumentation and Measurement Soc., Keysight Technologies: Downloaded on May 26, 2023 at 01:47:28 UTC from IEEE Xplore, pp. 1-6. [cited by applicant]
Ethernet Synchronization, Keysight Technologies, Jun. 24, 2020, 7019-0048.EN pp. 1-207. [cited by applicant]
“How to Configure DP83867 SFDs,” Texas Instruments Application Report—SNLA242—Oct. 2015, pp. 1-7. [cited by applicant]
“100GE and 40GE PCS Overview,” Generic Architecture, Nicholl, IEEE 802.3az, Nov. 2008 Dallas, pp. 1-27. [cited by applicant]
Notice of Allowance and Fee(s) Due for U.S. Appl. No. 10/789,697 (Oct. 12, 2005). [cited by applicant]
Non-Final Office Action for U.S. Appl. No. 10/789,697 (Jul. 25, 2005). [cited by applicant]
Notice of Allowance and Fee(s) Due for U.S. Appl. No. 15/284,109 (Nov. 13, 2017). [cited by applicant]
Non-Final Office Action for U.S. Appl. No. 15/284,109 (Jul. 3, 2017). [cited by applicant]
“25 Gigabit Ethernet,” Wikipedia, https://en.wikipedia.org/wiki/25_Gigabit Ethernet, accessed through wayback machine, pp. 1-3 (Oct. 2, 2016). [cited by applicant]
“25Gb Ethernet: Accelerated Network Performance and Lower Costs for Enterprise Data Center and Cloud Environments,” White Paper, QLogic a Cavium Company, SN0530917-00 Rev. D, pp. 1-7 (2016). [cited by applicant]
“Enabling 100 Gigabit Ethernet Implementing PCS Lanes,” Ixia, White Paper, 915-0909-01 Rev. C, pp. 1-11 (Jan. 2014). [cited by applicant]
Merritt, “Xilinx Marshals 10-Gbit serdes spec,” EETimes, http://www.eetimes.com/document.asp?doc_id=1145377, pp. 1-3 (Dec. 13, 2002). [cited by applicant]
Cited By (1)
US 12,726,426