Methods, systems, and computer readable media for characterizing a timestamping behavior of a device under test (DUT)
A method for characterizing a timestamping behavior of a device under test (DUT) includes, at a test system, transmitting packets to and receiving packets from the DUT. The test system controls transmit (Tx) timestamping of the packets transmitted to the DUT or receive (Rx) timestamping of the packets received from the DUT. The test system determines based on the Tx and Rx timestamping, timing measurements of the packets transmitted to the DUT and the packets received from the DUT. The test system uses the timing measurements to identify and characterize a timestamping behavior of the DUT.
1 . A method for characterizing a timestamping behavior of a device under test (DUT), the method comprising:
at a test system, transmitting packets to and receiving packets from the DUT;
controlling, by the test system, transmit (Tx) timestamping of the packets transmitted to the DUT or receive (Rx) timestamping of the packets received from the DUT;
determining, by the test system and based on the Tx and Rx timestamping, timing measurements of the packets transmitted to the DUT and the packets received from the DUT, wherein determining the timing measurements includes determining delay measurements of the packets transmitted to and the packets received from the DUT; and
using the timing measurements to identify and characterize a timestamping behavior of the DUT, wherein using the timing measurements to characterize a timestamping behavior of the DUT includes determining a periodicity of the delay measurements and using changes in the periodicity to determine when a physical layer chip causes changes in the Rx timestamping or Tx timestamping of the DUT.
2 . The method of claim 1 wherein controlling the Tx timestamping of packets transmitted to the DUT or the Rx timestamping of the packets received from the DUT comprises controlling the Tx timestamping of the packets transmitted to the DUT.
3 . The method of claim 1 wherein controlling the Tx timestamping of packets transmitted to the DUT or the Rx timestamping of the packets received from the DUT comprises controlling the Rx timestamping of the packets received from the DUT.
4 . The method of claim 1 wherein using changes in the periodicity to determine when the physical layer chip causes changes in the Rx timestamping or Tx timestamping of the DUT includes correlating the changes in periodicity with insertion of symbols into a physical layer bit stream.
5 . The method of claim 4 wherein correlating the timestamping behavior with the insertion of symbols includes correlating the timestamping behavior with the insertion of lane markers, forward error correction (FEC), and/or parity bits into the physical layer bit stream.
6 . The method of claim 5 wherein transmitting packets to the DUT includes transmitting the packets in a manner that causes the DUT to insert the lane markers, FEC bits, and/or parity bits into the physical layer bit stream.
7 . The method of claim 1 wherein characterizing the timestamping behavior of the DUT includes characterizing the Tx timestamping behavior of the DUT.
8 . The method of claim 1 wherein characterizing the timestamping behavior of the DUT includes characterizing the Rx timestamping behavior of the DUT.
9 . A system for characterizing a timestamping behavior of a device under test (DUT), the system comprising:
a test system configured for:
transmitting packets to and receiving packets from the DUT;
controlling transmit (Tx) timestamping of the packets transmitted to the DUT or receive (Rx) timestamping of the packets received from the DUT;
determining, based on the Tx and Rx timestamping, timing measurements of the packets transmitted to the DUT and the packets received from the DUT, wherein determining the timing measurements includes determining delay measurements of the packets transmitted to and the packets received from the DUT; and
using the timing measurements to identify and characterize a timestamping behavior of the DUT, wherein using the timing measurements to characterize a timestamping behavior of the DUT includes determining a periodicity of the delay measurements and using changes in the periodicity to determine when a physical layer chip causes changes in the Rx timestamping or Tx timestamping of the DUT.
10 . The system of claim 9 wherein controlling the Tx timestamping of packets transmitted to the DUT or the Rx timestamping of the packets received from the DUT comprises controlling the Tx timestamping of the packets transmitted to the DUT.
11 . The system of claim 9 wherein controlling the Tx timestamping of packets transmitted to the DUT or the Rx timestamping of the packets received from the DUT comprises controlling the Rx timestamping of the packets received from the DUT.
12 . The system of claim 11 wherein using changes in the periodicity to determine when the physical layer chip causes changes in the Rx timestamping or the Tx timestamping of the DUT includes correlating the changes in periodicity with insertion of symbols into a physical layer bit stream.
13 . The system of claim 12 wherein correlating the timestamping behavior with the insertion of symbols includes correlating the timestamping behavior with the insertion of lane markers, forward error correction (FEC), and/or parity bits into the physical layer bit stream.
14 . The system of claim 13 wherein transmitting packets to the DUT includes transmitting the packets in a manner that causes the DUT to insert the lane markers, FEC bits, and/or parity bits into the physical layer bit stream.
15 . The system of claim 9 wherein characterizing the timestamping behavior of the DUT includes characterizing the Tx or Rx timestamping behavior of the DUT.
16 . A non-transitory computer readable medium having stored thereon executable instructions that when executed by at least one processor of at least one computer cause the at least one computer to perform steps comprising:
transmitting packets to and receiving packets from the DUT;
controlling transmit (Tx) timestamping of the packets transmitted to the DUT or receive (Rx) timestamping of the packets received from the DUT;
determining, based on the Tx and Rx timestamping, timing measurements of the packets transmitted to the DUT and the packets received from the DUT, wherein determining the timing measurements includes determining delay measurements of the packets transmitted to and the packets received from the DUT; and
using the timing measurements to identify and characterize a timestamping behavior of the DUT, wherein using the timing measurements to characterize a timestamping behavior of the DUT includes determining a periodicity of the delay measurements and using changes in the periodicity to determine when a physical layer chip causes changes in the Rx timestamping or Tx timestamping of the DUT.