Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars
According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.
1. A semiconductor memory device comprising:
a first stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a memory region, a stepped region, and a connection region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers;
a contact portion that is disposed in the connection region and electrically connects structures disposed above and below the first stacked body to each other;
a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction, and forms a memory cell at each intersection with at least a part of the plurality of conductive layers;
a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region, in the stacking direction, the plurality of conductive layers being processed in a stepped shape in the stepped portion; and
a plurality of third pillars that extends in the first stacked body in the stacking direction and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.
2. The semiconductor memory device according to claim 1 , wherein
each of the plurality of second pillars has a single layer structure of the second insulating layer, and
each of the plurality of third pillars includes
a core material of an insulator extending in the stacking direction,
a semiconductor layer covering a side wall of the core material, and
a third insulating layer covering a side wall of the semiconductor layer and containing a different kind of material from that of the second insulating layer.
3. The semiconductor memory device according to claim 2 , wherein
the second insulating layer is an oxide layer, and
the third insulating layer includes an oxide layer and a nitride layer.
4. The semiconductor memory device according to claim 1 , wherein
the plurality of second pillars is disposed, in the position overlapping the stepped portion, to overlap a portion where lower conductive layers of the first stacked body among the plurality of conductive layers are processed in the stepped shape,
a first part of the plurality of third pillars corresponding to the at least part of the plurality of third pillars is disposed in the connection region, and
a second part of the plurality of third pillars is disposed, in the position overlapping the stepped portion, to overlap a portion where upper conductive layers of the first stacked body among the plurality of conductive layers are processed in the stepped shape, and extends in the stacking direction.
5. The semiconductor memory device according to claim 4 , further comprising
an isolation layer that penetrates through an uppermost conductive layer among the plurality of conductive layers or penetrates through the uppermost conductive layer and one or more conductive layers continuous to the uppermost conductive layer among the plurality of conductive layers in the stacking direction and selectively isolates one or more upper conductive layers among the plurality of conductive layers in a second direction intersecting the stacking direction and the first direction, wherein
the second part of the plurality of third pillars is disposed to overlap a portion where the one or more upper conductive layers penetrated by the isolation layer are processed in the stepped shape.
6. The semiconductor memory device according to claim 5 , wherein
a third part of the plurality of third pillars is disposed, in the position overlapping the stepped portion, to overlap a portion where one or more conductive layers that are positioned below the one or more upper conductive layers and are continuous to a lowermost conductive layer of the one or more upper conductive layers in the stacking direction among the plurality of conductive layers are processed in the stepped shape, and extends in the stacking direction.
7. The semiconductor memory device according to claim 4 , wherein
the contact portion includes a second stacked body that includes a plurality of fourth insulating layers and the plurality of first insulating layers alternately stacked one by one, and is surrounded by the first stacked body in which the third pillars are dispersedly arranged when viewed from the stacking direction.
8. The semiconductor memory device according to claim 7 , wherein
the contact portion further includes a plurality of through contacts that extends in the second stacked body in the stacking direction and electrically connects the structures disposed above and below the first stacked body, and
none of the second and third pillars is disposed between the through contacts.
9. The semiconductor memory device according to claim 1 , wherein
the plurality of second pillars is dispersedly arranged over the entire stepped region.
10. The semiconductor memory device according to claim 1 , further comprising
a plate member that extends in the first stacked body in the stacking direction and the first direction and divides the first stacked body in a second direction intersecting the stacking direction and the first direction, wherein
the stepped portion includes
a first stepped portion disposed on one side of the plate member in the second direction, and
a second stepped portion disposed on the other side of the plate member in the second direction,
the contact portion includes
a first contact portion disposed on the one side of the plate member in the second direction, and
a second contact portion disposed on the other side of the plate member in the second direction,
the first stepped portion and the second contact portion are arranged side by side in the second direction with the plate member interposed therebetween, and
the second stepped portion and the first contact portion are arranged side by side in the second direction with the plate member interposed therebetween.
11. The semiconductor memory device according to claim 10 , wherein
the stepped region includes
a first stepped region including the first stepped portion and covered with a fifth insulating layer at least up to a height position corresponding to an uppermost layer of the first stacked body, and
a second stepped region including the second stepped portion and covered with the fifth insulating layer at least up to a height position corresponding to the uppermost layer of the first stacked body, and
the plate member includes
a first plate member extending in the first direction at a position between the first and second stepped portions, and
a second plate member extending in the first direction at a position that is opposite to the first plate member in the second direction with respect to the first stepped portion and overlaps the first stepped region, and dividing the fifth insulating layer in the second direction.
12. A semiconductor memory device comprising:
a first stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a stepped portion in which the plurality of conductive layers is processed in a stepped shape;
a plurality of first pillars that extends in a stacking direction of the first stacked body in the first stacked body in a position away from the stepped portion in a first direction intersecting the stacking direction and forms a memory cell at each intersection with at least a part of the plurality of conductive layers;
a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a portion where lower conductive layers of the first stacked body among the plurality of conductive layers are processed in the stepped shape; and
a plurality of third pillars that extends in the first stacked body in the stacking direction and has the same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in a position overlapping a portion where upper conductive layers of the first stacked body among the plurality of conductive layers are processed in the stepped shape.
13. The semiconductor memory device according to claim 12 , wherein
each of the plurality of second pillars has a single layer structure of the second insulating layer, and
each of the plurality of third pillars includes
a core material of an insulator extending in the stacking direction,
a semiconductor layer covering a side wall of the core material, and
a third insulating layer covering a side wall of the semiconductor layer and containing a different kind of material from that of the second insulating layer.
14. The semiconductor memory device according to claim 13 , wherein
the second insulating layer is an oxide layer, and
the third insulating layer includes an oxide layer and a nitride layer.
15. The semiconductor memory device according to claim 12 , further comprising
an isolation layer that penetrates through an uppermost conductive layer among the plurality of conductive layers or penetrates through the uppermost conductive layer and one or more conductive layers continuous to the uppermost conductive layer among the plurality of conductive layers in the stacking direction and selectively isolates one or more upper conductive layers among the plurality of conductive layers in a second direction intersecting the stacking direction and the first direction, wherein
at least a part of the plurality of third pillars is disposed to overlap a portion where the one or more upper conductive layers penetrated by the isolation layer are processed in the stepped shape, and extends in the stacking direction.
16. The semiconductor memory device according to claim 15 , wherein
at least another part of the plurality of third pillars is disposed to overlap a portion where one or more conductive layers that are positioned below the one or more upper conductive layers and are continuous to a lowermost conductive layer of the one or more upper conductive layers in the stacking direction among the plurality of conductive layers are processed in the stepped shape, and extends in the stacking direction.
17. The semiconductor memory device according to claim 12 , further comprising
a second stacked body that includes a plurality of fourth insulating layers and the plurality of first insulating layers alternately stacked one by one and is surrounded by the first stacked body when viewed from the stacking direction, wherein
another part of the plurality of third pillar other than the at least part of the plurality of third pillars extends in the stacking direction in the first stacked body surrounding the second stacked body.
18. The semiconductor memory device according to claim 12 , wherein
the plurality of second pillars is dispersedly arranged in the position overlapping the portion where the lower conductive layers are processed in the stepped shape, and
the plurality of third pillars is dispersedly arranged in the position overlapping the portion where the upper conductive layers are processed in the stepped shape.
19. The semiconductor memory device according to claim 18 , further comprising
a fifth insulating layer that covers the stepped portion at least up to a height position corresponding to an uppermost layer of the first stacked body; and
a plate member that extends in the first stacked body in the stacking direction and the first direction and is in contact with the fifth insulating layer in a second direction intersecting the stacking direction and the first direction.
20. The semiconductor memory device according to claim 18 , further comprising
a fifth insulating layer that covers the stepped portion at least up to a height position corresponding to an uppermost layer of the first stacked body; and
a plurality of contacts that penetrates through the fifth insulating layer and is connected to the plurality of conductive layers in the stepped portion.