IP Library › Granted Patent US 12,386,690
Granted Patent B2
US 12,386,690 · App. 18/406,922 · Granted Aug 12, 2025

Fail data augmentation device and method for random access memory

Inventors: Seung Yeol Lee (Gyeonggi-do, KR); Jung Soo Kim (Gyeonggi-do, KR); Chang Hoon Lee (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F11/079G06F11/073
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,386,690
App. No.
18/406,922
Granted
Aug 12, 2025
Kind
B2
Abstract

A fail data augmentation device may input a plurality of fail data units to a data augmentation model, obtain a plurality of augmented fail data units outputted from the data augmentation model, and delete one or more of the augmented fail data units. The plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of a plurality of banks included in a random access memory, a second parameter indicating one of a plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of a plurality of hex units included in the matrix corresponding to the second parameter respectively.

Claims (55)

1. A fail data augmentation device comprising:

a memory configured to store a plurality of fail data units for a target random access memory and a data augmentation model that inputs the plurality of fail data units and outputs a plurality of augmented fail data units; and

a processor configured to execute instructions for:

inputting the plurality of fail data units to the data augmentation model,

obtaining the plurality of augmented fail data units output from the data augmentation model, and

deleting one or more of the plurality of augmented fail data units,

wherein the target random access memory includes a plurality of banks,

wherein each of the plurality of banks includes a plurality of matrices,

wherein each of the plurality of matrices include a plurality of hex units, and

wherein each of the plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of the plurality of banks, a second parameter indicating one of the plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of the plurality of hex units included in the matrix corresponding to the second parameter.

2. The fail data augmentation device according to claim 1 ,

wherein the data augmentation model includes a Synthetic Minority Over-sampling Technique (SMOTE) model or a Generative Adversarial Network (GAN) model.

3. The fail data augmentation device according to claim 1 ,

wherein each of the plurality of fail data units and the plurality of augmented fail data units includes at least one of a row address, a column address, channel information, main word line information, sub word line control signal, chip select information and data information.

4. The fail data augmentation device according to claim 1 ,

wherein the processor is configured to execute an instruction for deleting one or more of the plurality of augmented fail data units based on the first parameter, second parameter and third parameter of the plurality of augmented fail data units.

5. The fail data augmentation device according to claim 4 ,

wherein the processor is configured to execute an instruction for deleting one or more augmented fail data units, among the plurality of augmented fail data units, of which the first parameter is less than a first threshold or greater than a second threshold,

wherein the first threshold is a minimum value among first parameters of the plurality of fail data units, and

wherein the second threshold is a maximum value among first parameters of the plurality of fail data units.

6. The fail data augmentation device according to claim 5 ,

wherein the processor is configured to execute an instruction for deleting one or more augmented fail data units among the plurality of augmented fail data units, of which the second parameter is less than a third threshold or greater than a fourth threshold,

wherein the third threshold is a minimum value among second parameters of the plurality of fail data units, and

wherein the fourth threshold is a maximum value among second parameters of the plurality of fail data units.

7. The fail data augmentation device according to claim 6 ,

wherein the processor is configured to execute an instruction for deleting one or more augmented fail data units among the plurality of augmented fail data units, of which the third parameter is different from third parameters of the plurality of fail data units.

8. A fail data augmentation method comprising:

inputting a plurality of fail data units for a target random access memory to a data augmentation model;

obtaining a plurality of augmented fail data units output from the data augmentation model; and

deleting one or more of the plurality of augmented fail data units,

wherein the target random access memory includes a plurality of banks,

wherein each of the plurality of banks includes a plurality of matrices,

wherein each of the plurality of matrices include a plurality of hex units, and

wherein each of the plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of the plurality of banks, a second parameter indicating one of the plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of the plurality of hex units included in the matrix corresponding to the second parameter.

9. The fail data augmentation method of claim 8 ,

wherein the deleting one or more of the plurality of augmented fail data units comprises deleting one or more of the plurality of augmented fail data units based on the first parameter, second parameter and third parameter of the plurality of augmented fail data units.

10. The fail data augmentation method of claim 8 ,

wherein the deleting one or more of the plurality of augmented fail data units comprises deleting one or more augmented fail data units among the plurality of augmented fail data units, of which the first parameter is less than a first threshold or greater than a second threshold,

wherein the first threshold is a minimum value among first parameters of the plurality of fail data units, and

wherein the second threshold is a maximum value among first parameters of the plurality of fail data units.

11. The fail data augmentation method of claim 10 ,

wherein the deleting one or more of the plurality of augmented fail data units comprises deleting one or more augmented fail data units among the plurality of augmented fail data units, of which the second parameter is less than a third threshold or greater than a fourth threshold,

wherein the third threshold is a minimum value among second parameters of the plurality of fail data units, and

wherein the fourth threshold is a maximum value among second parameters of the plurality of fail data units.

12. The fail data augmentation method of claim 11 ,

wherein the deleting one or more of the plurality of augmented fail data units comprises deleting one or more augmented fail data units, among the plurality of augmented fail data units, of which the third parameter is different from third parameters of the plurality of fail data units.

13. A fail data augmentation device comprising:

a memory configured to store a plurality of fail data units for a target random access memory and a data augmentation model; and

a processor configured to:

input a plurality of fail data units into a data augmentation model;

obtain a plurality of augmented fail data units output from the data augmentation model, and

delete one or more of the plurality of augmented fail data units,

wherein the target random access memory includes several memory areas with a hierarchy,

wherein each of the plurality of fail data units and the plurality of augmented fail data units includes several parameter values corresponding to respective memory areas,

wherein the one or more of the plurality of augmented fail data units are deleted according to threshold ranges which are preset for each memory areas and each parameter value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2024
From: LEE, SEUNG YEOL; KIM, JUNG SOO; LEE, CHANG HOON
To: SK HYNIX INC.
Reel/Frame 066053/0486 →
Priority Claims (1)
KR 10-2023-0109768 · Aug 22, 2023 · national
Continuity (1)
Related Publication 20250068500A1 · Feb 27, 2025
References Cited (13)
US 5349579A · Madonna · 1994 [cited by examiner]
US 11170585B2 · Sankavaram et al. · 2021 [cited by applicant]
US 20140064247A1 · Teyeb · 2014 [cited by examiner]
US 20210049452A1 · Fan · 2021 [cited by examiner]
US 20230161655A1 · Schlichting · 2023 [cited by examiner]
US 20240071506A1 · Xu · 2024 [cited by examiner]
US 20240143993A1 · Schneuwly · 2024 [cited by examiner]
US 20240176714A1 · Diao · 2024 [cited by examiner]
US 20240281718A1 · Lai · 2024 [cited by examiner]
US 20240345914A1 · Selvaraj · 2024 [cited by examiner]
US 20250036509A1 · We · 2025 [cited by examiner]
US 20250036514A1 · Gu · 2025 [cited by examiner]
KR 20190142540A · 2019 [cited by applicant]