IP Library Granted Patent US 12,387,930
Granted Patent B2
US 12,387,930 · App. 18/153,282 · Granted Aug 12, 2025

Method and wafer processing furnace for forming an epitaxial stack of semiconductor epitaxial layers on a plurality of substrates

Inventors: Dieter Pierreux (Pepingen, BE); Kelly Houben (Lubbeek, BE); Steven Van Aerde (Tielt-Winge, BE); Wilco Verweij (Nijkerk, BE); Bert Jongbloed (Oud-Heverlee, BE); Charles Dezelah (Helsinki, FI)
Assignee: ASM IP Holding B.V.
H01L21/0262C30B25/165C30B25/186C30B29/06C30B29/52C30B29/68H01L21/02532H01L21/02661
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Quick Facts
Patent No.
US 12,387,930
App. No.
18/153,282
Granted
Aug 12, 2025
Kind
B2
Abstract

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer.

Claims (32)

1. A method of forming an epitaxial stack on a plurality of substrates; the method comprising

providing the plurality of substrates to a process chamber;

executing a plurality of deposition cycles, thereby forming the epitaxial stack on the plurality of substrates, the epitaxial stack comprising a plurality of epitaxial pairs, wherein the epitaxial pairs each comprise a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer, wherein a deposition cycle comprises:

a first deposition pulse comprising a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer; and

a second deposition pulse comprising a provision of a second reaction gas mixture to the process chamber, the second reaction gas mixture being different from the first reaction gas mixture, thereby forming the second epitaxial layer,

wherein the first deposition pulse is carried out at a first deposition temperature;

wherein the second deposition pulse is carried out at a second deposition temperature;

wherein the first deposition temperature is different from the second deposition temperature by at most 50° C.; and

wherein the forming of the first epitaxial layer comprises forming the first epitaxial layer on both sides of the plurality of substrates.

2. The method according to claim 1 , wherein:

the first epitaxial layer comprises a first semiconductor material;

the provision of the first reaction gas mixture comprises providing first semiconductor material precursors;

the second epitaxial layer comprises a second semiconductor material being different than the first semiconductor material; and

the provision of the second reaction gas mixture comprises providing a second semiconductor material precursor.

3. The method according to claim 2 , wherein the first semiconductor material precursors comprise a germanium-containing compound and a first silicon-containing compound; and

wherein the second semiconductor material precursor comprises substantially a second silicon-containing compound.

4. The method according to claim 3 , wherein the germanium-containing compound comprised in the first semiconductor material precursors is at least one of GeH4 and GeCl4.

5. The method according to claim 3 , wherein the second silicon-containing compound comprised substantially in the second semiconductor material precursor is trisilane.

6. The method according to claim 5 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors is trisilane.

7. The method according to claim 3 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors is a cyclic silane or a high order branched silane; and

wherein the germanium-containing compound comprised in the first semiconductor material precursors is GeH4.

8. The method according to claim 7 , wherein the cyclic silane is cyclohexasilane.

9. The method according to claim 7 , wherein the high order branched silane is neopentasilane.

10. The method according to claim 1 , wherein both the first and the second deposition temperature is at a temperature in a range of 300° C.° to 550° C.

11. The method according to claim 5 , wherein the first silicon-containing compound is provided in a continuous flow; and

wherein the germanium-containing compound is provided intermittently.

12. The method according to claim 5 , wherein the germanium-containing compound comprised in the first semiconductor material precursors is GeH4; and

wherein the first silicon-containing compound comprised in the first semiconductor material precursors is mono silane.

13. The method according to claim 1 , wherein the method further comprises, before executing the plurality of deposition cycles, performing a pre-cleaning step, the pre-cleaning step comprising subjecting both the sides of the plurality of substrates to an ambient comprising a fluorine-containing compound.

14. The method according to claim 13 , further comprising subjecting the plurality of substrates to a Cl comprising ambient at a temperature in a range of 400° C.-600° C. after subjecting both the sides of the plurality of substrates to the ambient comprising the fluorine-containing compound.

15. The method according to claim 1 , wherein at least one of the first reaction gas mixture and the second reaction gas mixture comprises an etchant gas.

16. The method according to claim 1 , wherein the process chamber is comprised in a vertical furnace.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2023
From: PIERREUX, DIETER; HOUBEN, KELLY; VAN AERDE, STEVEN; VERWEIJ, WILCO; JONGBLOED, BERT; DEZELAH, CHARLES
To: ASM IP HOLDING B.V.
Reel/Frame 062492/0985 →
Continuity (2)
Provisional Application 63299184 · Jan 13, 2022
Related Publication 20230223258A1 · Jul 13, 2023
References Cited (9)
US 5821155A · Izumi · 1998 [cited by examiner]
US 10510871B1 · More · 2019 [cited by applicant]
US 20110003451A1 · Orlowski · 2011 [cited by applicant]
US 20160049489A1 · Wan · 2016 [cited by examiner]
US 20210057570A1 · Lin · 2021 [cited by applicant]
US 20210118679A1 · Barbosa Lima · 2021 [cited by examiner]
US 20210327704A1 · Kajbafvala · 2021 [cited by examiner]
EP 2005112577 · 2005 [cited by examiner]
WO WO2005112577A2 · 2005 [cited by examiner]