Device chip scale package including a protective layer and method of manufacturing a device chip scale package
In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.
1. A method to manufacture a semiconductor device, comprising:
providing a redistribution layer (RDL) substrate comprising a top side, a bottom side opposite the top side, and a conductive layer, wherein the conductive layer includes a plurality of pads, the plurality of pads including a first portion below the top side of the RDL substrate and a second portion protruding above the top side of the RDL substrate;
disposing an electronic device on the plurality of pads;
providing a first protective material over a lateral side of the electronic device and the top side of the RDL substrate;
providing a conductive post on the bottom side of the RDL substrate using a first plating operation;
providing a base structure on the bottom side of the RDL substrate, the base structure comprising a second protective material covering a lateral side of the conductive post and the bottom side of the RDL substrate;
providing a base layer on a bottom side of the conductive post, wherein a lateral side of the base layer is exposed; and
providing an external interconnect on a bottommost side of the base layer and coupled with the conductive post, wherein the external interconnect is coupled with the conductive post through an opening in the base layer.
2. The method of claim 1 , wherein providing the external interconnect on the base layer comprises:
providing a pillar on the base layer using a second plating operation; and
providing a solder cap on the pillar.
3. The method of claim 1 , wherein the base layer comprises a conductive material.
4. The method of claim 1 , wherein:
the RDL substrate is provided on a first carrier; and
further comprising:
attaching a second carrier to the first protective material; and
removing the first carrier from the RDL substrate to expose the bottom side of the RDL substrate and the conductive layer.
5. The method of claim 4 , wherein the first carrier is removed using a grinding or etching operation.
6. The method of claim 4 , wherein providing the external interconnect on the base layer comprises:
providing a pillar on the base layer using a second plating operation; and
providing a solder cap on the pillar; and
further comprising removing the second carrier after the solder cap is provided.
7. The method of claim 1 , wherein:
the second protective material is provided in a first molding operation; and
the first protective material is provided in a second molding operation.
8. A method to manufacture a semiconductor device, comprising:
providing a redistribution layer (RDL) substrate having a top side and a bottom side, wherein the RDL substrate comprises a filler-free dielectric material, and wherein the RDL substrate comprises a conductive layer exposed from the bottom side, and wherein the conductive layer includes a plurality of pads, the plurality of pads including a first portion below the top side of the RDL substrate and a second portion protruding above the top side of the RDL substrate;
providing an electronic device on the plurality of pads;
providing a conductive post on the bottom side of the RDL substrate and electrically coupled to the electronic device;
providing a first protective material over a lateral side of the electronic device and the top side of the RDL substrate;
providing a base structure on the bottom side of the RDL substrate, the base structure comprising a second protective material on a lateral side of the conductive post and the bottom side of the RDL substrate; and
providing an external interconnect below a bottom side of the base structure to couple with the conductive post, wherein the external interconnect is coupled with the conductive post through an opening in the base structure, wherein the external interconnect directly contacts the conductive post.
9. The method of claim 8 , wherein the external interconnect comprises a conductive pillar and an interconnect tip on the conductive pillar.
10. The method of claim 8 , wherein the external interconnect comprises a conductive pillar and a conductive bump on the conductive pillar.
11. The method of claim 8 , wherein the external interconnect comprises a solder ball.
12. The method of claim 8 , wherein the RDL substrate comprises a dielectric layer.
13. The method of claim 8 , wherein the first protective material and the second protective material comprise a same material having a same coefficient of thermal expansion (CTE).
14. The method of claim 8 , wherein the first protective material and the second protective material comprise different materials having a same coefficient of thermal expansion (CTE).
15. The method of claim 8 , wherein the first protective material has a first coefficient of thermal expansion (CTE) and a first thickness, and the second protective material has a second CTE and a second thickness such that warpage between the first protective material and the RDL substrate counters warpage between the second protective material and the RDL substrate.
16. The method of claim 8 , wherein:
the second protective material is provided in a first molding operation; and
the first protective material is provided in a second molding operation.
17. A semiconductor device, comprising:
a redistribution layer (RDL) substrate comprising a top side, a bottom side opposite the top side, and a conductive layer, wherein the conductive layer includes a plurality of pads, the plurality of pads including a first portion below the top side of the RDL substrate and a second portion protruding above the top side of the RDL substrate;
an electronic device on the plurality of pads;
a first protective material over a lateral side of the electronic device and the top side of the RDL substrate;
a conductive post on the bottom side of the RDL substrate using a first plating operation;
a base structure on the bottom side of the RDL substrate, the base structure comprising a second protective material covering a lateral side of the conductive post and the bottom side of the RDL substrate;
a base layer on a bottom side of the conductive post, wherein a lateral side of the base layer is exposed; and
an external interconnect on a bottommost side of the base layer and coupled with the conductive post, wherein the external interconnect is coupled with the conductive post through an opening in the base layer.
18. The semiconductor device of claim 17 , wherein the external interconnect on the base layer comprises:
a pillar on the base layer; and
a solder cap on the pillar.
19. The semiconductor device of claim 18 , wherein the pillar extends beyond a bottom side of the second protective material.
20. The semiconductor device of claim 17 , wherein the base layer comprises a conductive material.