Flip-flop cell
An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
1. A flip-flop structure defined as a standard cell stored in a cell library, the flip-flop structure comprising:
a substrate defining an outer periphery comprising a first border, a second border, a third border, and a fourth border, wherein the first border is opposite and parallel to the second border, wherein the third border being opposite and parallel to the fourth border;
a first clock input terminal positioned so as to extend to the first border;
a second clock input terminal positioned so as to extend to the third border;
a first clock output terminal positioned so as to extend to the second border, wherein the first clock output terminal propagates a clock signal received at the first clock input terminal to a first flip-flop abutting the second border; and
a second clock output terminal positioned so as to extend to the fourth border, wherein the second clock output terminal propagates the clock signal received at the first clock input terminal to a second flip-flop abutting the fourth border.
2. The flip-flop structure of claim 1 , wherein the second border is a bottom border and the first border is a top border.
3. The flip-flop structure of claim 1 , wherein the third border is a first side border and the fourth border is a second side border.
4. The flip-flop structure of claim 1 , wherein the flip-flop structure comprises a single bit flip-flop of a multi-bit flip-flop.
5. The flip-flop structure of claim 1 , further comprising an amplifier configured to amplify clock pulse received at the first clock input terminal.
6. The flip-flop structure of claim 5 , wherein the amplifier propagates the amplified clock pulse to the first clock output terminal.
7. The flip-flop structure of claim 1 , wherein the first clock input terminal and the first clock output terminal form a first clock propagation path in a first direction, and wherein the first clock input terminal and the second clock output terminal form a second clock propagation path in a second direction, the second direction being orthogonal to the first direction.
8. A flip-flop structure defined as a standard cell stored in a cell library, comprising:
a substrate defining an outer periphery having a first border, a second border, a third border, and a fourth border;
a first clock input terminal positioned so as to extend to the first border;
a second clock input terminal positioned so as to extend to the third border;
a first clock output terminal positioned so as to extend to the second border, wherein the first clock output terminal propagates a clock signal received at the first clock input terminal to a first flip-flop abutting the second border; and
a second clock output terminal positioned so as to extend to the fourth border.
9. The flip-flop structure of claim 8 , wherein the first clock input terminal and the first clock output terminal form a first clock propagation path in a first direction, and wherein the second clock input terminal and the second clock output terminal form a second clock propagation path in a second direction, the second direction being orthogonal to the first direction.
10. The flip-flop structure of claim 8 , further comprising an amplifier configured to amplify clock pulse received at the first clock input terminal.
11. The flip-flop structure of claim 10 , wherein the amplifier propagates the amplified clock pulse to the first clock output terminal and the second clock output terminal.
12. The flip-flop structure of claim 8 , wherein the flip-flop structure comprises a single bit flip-flop of a multi-bit flip-flop.
13. The flip-flop structure of claim 8 , wherein the flip-flop structure comprises a Standard Threshold Voltage (SVT) device.
14. The flip-flop structure of claim 8 , wherein the flip-flop structure comprises a Low Threshold Voltage (LVT) device.
15. The flip-flop structure of claim 8 , wherein the flip-flop structure comprises an Ultra Low Threshold Voltage (ULVT) device.
16. A flip-flop structure defined as a standard cell stored in a cell library, comprising a substrate defining an outer periphery having a first border, a second border, a third border, and a fourth border;
a first clock input terminal positioned so as to extend to the first border;
a second clock input terminal positioned so as to extend to the third border;
a first clock output terminal positioned so as to extend to the second border; and
a second clock output terminal positioned so as to extend to the fourth border, wherein each of the third border and the fourth border are perpendicular to each of the first border and the second border, wherein the second clock output terminal propagates a clock signal received at the first clock input terminal to a first flip-flop abutting the fourth border.
17. The flip-flop structure of claim 16 , wherein the second border is a bottom border and the first border is a top border.
18. The flip-flop structure of claim 16 , wherein the third border is a first side border and the fourth border is a second side border.
19. The flip-flop structure of claim 16 , wherein the flip-flop structure comprises a single bit flip-flop of a multi-bit flip-flop.