Method of forming fully strained channels
A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.
1. A semiconductor structure, comprising:
a substrate;
a first fin extending from the substrate, wherein the first fin includes a bottom portion and an upper portion over the bottom portion, the upper portion and the bottom portion include different materials, and the upper portion includes silicon germanium; and
an alignment mark over the substrate and having one or more dielectric layers extending above a top surface of the substrate, wherein a top surface of the first fin is substantially coplanar with a top surface of the one or more dielectric layers,
wherein the bottom portion of the first fin is an N well portion of the substrate, and a bottom surface of the N well portion is substantially coplanar with a bottom surface of the alignment mark.
2. The semiconductor structure of claim 1 , wherein the alignment mark partially extends into the substrate.
3. The semiconductor structure of claim 1 , wherein the alignment mark includes a bottom portion and a top portion over the bottom portion, the bottom portion having a first dielectric layer and the top portion having a second dielectric layer over the first dielectric layer.
4. The semiconductor structure of claim 3 , wherein the first dielectric layer has a top surface substantially coplanar with a top surface of the substrate.
5. The semiconductor structure of claim 1 , wherein a bottom portion of the alignment mark is embedded in a P well portion of the substrate.
6. The semiconductor structure of claim 5 , wherein the first fin further includes a silicon seed layer between the bottom portion and the upper portion of the first fin.
7. The semiconductor structure of claim 1 , further comprising a second fin extending from the substrate, wherein the second fin includes a bottom portion and an upper portion over the bottom portion, the bottom portion and the upper portion of the second fin include silicon.
8. The semiconductor structure of claim 7 , wherein the bottom portion of the second fin is a P well portion of the substrate.
9. The semiconductor structure of claim 1 , further comprising an isolation structure over the substrate, the isolation structure surrounds the bottom portion of the first fin.
10. A semiconductor structure, comprising:
a substrate;
a first fin extending from the substrate, wherein the first fin includes a bottom portion and an upper portion over the bottom portion, the upper portion and the bottom portion include different semiconductor materials, and the upper portion includes silicon germanium;
an isolation structure over the substrate, wherein a top surface of the isolation structure is substantially coplanar with a top surface of the bottom portion of the first fin; and
an alignment mark over the substrate, the alignment mark having a bottom portion and a top portion, the bottom portion of the alignment mark is adjacent to the isolation structure, and the top portion of the alignment mark extends above the top surface of the isolation structure, wherein the top portion of the alignment mark spans a greater lateral width than the bottom portion of the alignment mark, and the top portion of the alignment mark is laterally surrounded by a semiconductor material different from that of the upper portion of the first fin.
11. The semiconductor structure of claim 10 ,
wherein the bottom portion of the alignment mark includes silicon oxide,
wherein the top portion of the alignment mark includes silicon oxide and a bottom anti-reflective coating (BARC) material.
12. The semiconductor structure of claim 10 ,
wherein the bottom portion of the first fin is doped with an n-type dopant and the upper portion of the first fin is free of the n-type dopant.
13. The semiconductor structure of claim 10 , further comprising:
a second fin extending from the substrate, wherein the second fin includes a bottom portion and an upper portion over the bottom portion, the upper portion and the bottom portion of the second fin include silicon, wherein the bottom portion of the second fin is doped with a p-type dopant and the upper portion of the second fin is free of the p-type dopant.
14. The semiconductor structure of claim 13 , further comprising:
n-type source/drain features directly on the upper portion of the first fin; and
p-type source/drain features directly on the upper portion of the second fin.
15. The semiconductor structure of claim 13 ,
wherein the top surface of the isolation structure is substantially coplanar with a top surface of the bottom portion of the second fin.
16. The semiconductor structure of claim 10 , wherein the bottom portion and the top portion of the alignment mark both includes silicon oxide.
17. A semiconductor structure, comprising:
a substrate;
a first fin extending from the substrate, wherein the first fin includes a bottom portion and an upper portion over the bottom portion, the upper portion and the bottom portion of the first fin include different material compositions, and the upper portion of the first fin includes silicon germanium, wherein a silicon seed layer is disposed between the bottom portion and the upper portion of the first fin; and
a second fin extending from the substrate, wherein the second fin includes a bottom portion and an upper portion over the bottom portion, the upper portion and the bottom portion of the second fin include different material compositions, and the upper portion of the second fin includes silicon;
an isolation structure between the bottom portions of the first fin and the second fin; and
an alignment mark having one or more dielectric layers over the substrate and above the isolation structure, wherein the one or more dielectric layers spans from below a bottom surface of the isolation structure to a top surface of the first and second fins,
wherein a top portion of the alignment mark spans a greater lateral width than the bottom portion of the alignment mark, and the top portion of the alignment mark is laterally surrounded by a same semiconductor material as the silicon seed layer,
wherein the bottom portion of the first fin includes n-type dopants, and the upper portion of the first fin is free of the n-type dopants, and a bottom surface of the bottom portion of the first fin is substantially coplanar with a bottom surface of the alignment mark.
18. The semiconductor structure of claim 17 ,
wherein the bottom portion of the second fin includes p-type dopants, and the upper portion of the second fin is free of the p-type dopants.
19. The semiconductor structure of claim 18 ,
wherein the isolation structure surrounds the bottom portions of the first and second fins.
20. The semiconductor structure of claim 17 ,
wherein top surfaces of the first and second fins are substantially coplanar with a top surface of the alignment mark.