IP Library Granted Patent US 12,389,665
Granted Patent B2
US 12,389,665 · App. 18/410,016 · Granted Aug 12, 2025

Semiconductor device structure

Inventors: Lin-Yu Huang (Hsinchu, TW); Sheng-Tsung Wang (Hsinchu, TW); Jia-Chuan You (Taoyuan, TW); Chia-Hao Chang (Hsinchu, TW); Tien-Lu Lin (Hsinchu, TW); Yu-Ming Lin (Hsinchu, TW); Chih-Hao Wang (Baoshan Township, Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D84/038H01L21/02532H01L21/32134H01L21/32139H10D30/6219H10D30/797H10D62/021H10D62/151H10D64/01H10D64/015H10D64/017H10D64/021H10D84/013H10D84/0135H10D84/0158H10D84/834H01L21/02164H01L21/31116
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Quick Facts
Patent No.
US 12,389,665
App. No.
18/410,016
Filed
Jan 11, 2024
Granted
Aug 12, 2025
Kind
B2
Art Unit
2898
USPC
257/288
Abstract

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Claims (52)

1. A semiconductor device structure, comprising:

a substrate;

a gate stack formed over the substrate;

a source/drain structure formed adjacent to the gate stack; and

a contact structure vertically overlapping the source/drain structure, wherein the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

2. The semiconductor device structure as claimed in claim 1 , wherein the contact structure has a second sidewall slopes downwardly from its top surface to a top surface of the source/drain structure.

3. The semiconductor device structure as claimed in claim 2 , further comprising:

a first dielectric structure covering the first sidewall of the source/drain structure; and

a second dielectric structure covering the second sidewall of the source/drain structure,

wherein a first sidewall of the first dielectric structure, a first sidewall of the second dielectric structure, and a third sidewall of the contact structure substantially aligned with each other in a top view.

4. The semiconductor device structure as claimed in claim 3 , wherein the first sidewall and the second sidewall of the contact structure connect to opposite sides of the third sidewall of the contact structure.

5. The semiconductor device structure as claimed in claim 3 , further comprising:

a liner layer in contact with the first sidewall of the first dielectric structure, the first sidewall of the second dielectric structure, and the third sidewall of the contact structure.

6. The semiconductor device structure as claimed in claim 5 , wherein the liner layer is laterally sandwiched between the contact structure and the gate stack and is in direct contact with the top surface of the source/drain structure.

7. The semiconductor device structure as claimed in claim 1 , further comprising:

a first cap layer formed over the gate stack; and

a second cap layer formed over the contact structure,

wherein an interface between the first cap layer and the gate stack is lower than an interface between the second cap layer and the contact structure.

8. A semiconductor device structure, comprising:

a gate stack longitudinally oriented along a first direction;

a first source/drain structure and a second source/drain structure formed at a first side and a second side of the gate stack respectively, wherein the first source/drain structure is substantially aligned with the second source/drain structure in a second direction;

a third source/drain structure formed at the first side of the gate stack and spaced apart from the first source/drain structure in the first direction;

a contact structure formed over the first source/drain structure, wherein both the first source/drain structure and the third source/drain structure are connected to the contact structure; and

a dielectric structure attached to the contact structure in the first direction, wherein a top portion of the dielectric structure is wider than a middle portion of the dielectric structure in a cross-sectional view along the first direction.

9. The semiconductor device structure as claimed in claim 8 , wherein the contact structure laterally protruding from opposite edges of the third source/drain structure in the first direction.

10. The semiconductor device structure as claimed in claim 8 , further comprising:

a liner layer longitudinally oriented along the first direction and laterally sandwiched between the contact structure and the gate stack along the second direction, wherein a dimension of the liner layer is greater than a dimension of the contact structure in the first direction.

11. The semiconductor device structure as claimed in claim 10 , wherein the dimension of the liner layer is greater than a sum of the dimension of the contact structure and a dimension of the dielectric structure in the first direction.

12. The semiconductor device structure as claimed in claim 8 , further comprising:

a first cap layer formed over the contact structure; and

a second cap layer formed over the gate stack,

wherein a width of the first cap layer is substantially equal to a width of the second cap layer in the second direction.

13. A semiconductor device structure, comprising:

a first semiconductor structure;

a gate stack formed over the first semiconductor structure;

gate spacers on sidewalls of the gate stack;

an isolation layer under the gate stack;

a first source/drain structure attached to the first semiconductor structure and adjacent to the gate stack;

a contact structure formed over the first source/drain structure;

a cap layer formed over the contact structure, wherein a top width of the cap layer is greater than a bottom width of the cap layer; and

a dielectric structure extending downwardly from a first sidewall of the cap layer to a second sidewall of the contact structure.

14. The semiconductor device structure as claimed in claim 13 , wherein a top surface of the dielectric structure is substantially level with a top surface of the cap layer, and a bottom surface of the dielectric structure is substantially level with a bottom surface of the contact structure.

15. The semiconductor device structure as claimed in claim 13 , wherein the first sidewall of the cap layer and the second sidewall of the contact structure have substantially a same slope.

16. The semiconductor device structure as claimed in claim 13 , further comprising:

a second semiconductor structure at a first side of the first semiconductor structure; and

a second source/drain structure attached to the second semiconductor structure and at the first side of the first source/drain structure,

wherein the contact structure has a third sidewall at the first side of the second source/drain structure and the second sidewall over the first source/drain structure.

17. The semiconductor device structure as claimed in claim 13 , wherein the contact structure is in contact with a top surface of the isolation layer.

18. The semiconductor device structure as claimed in claim 13 , wherein a bottom surface of the contact structure is lower than a bottom surface of the first source/drain structure.

19. The semiconductor device structure as claimed in claim 13 , further comprising:

a gate cap layer over the gate stack, wherein a vertical dimension of the gate cap layer is greater than a vertical dimension of the cap layer.

20. The semiconductor device structure as claimed in claim 8 , wherein a portion of the contact structure is sandwiched between the first source/drain structure and the third source/drain structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2024
From: HUANG, LIN-YU; WANG, SHENG-TSUNG; YOU, JIA-CHUAN; CHANG, CHIA-HAO; LIN, TIEN-LU; LIN, YU-MING; WANG, CHIH-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 066096/0880 →
Continuity (4)
Continuation 17818443 · Aug 9, 2022
Continuation 17120689 · Dec 14, 2020
Division 16571684 · Sep 16, 2019
Related Publication 20240178069A1 · May 30, 2024
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