Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer, forming two via holes and a trench in the first IMD layer, forming a metal layer in the two via holes and the trench for forming a metal interconnection and a spin orbit torque (SOT) layer, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first hard mask on the MTJ, forming a second hard mask on the first hard mask, forming a cap layer adjacent to the MTJ, and forming a second IMD layer around the cap layer.
1. A method for fabricating a semiconductor device, comprising:
forming a first inter-metal dielectric (IMD) layer on a substrate;
forming two via holes and a trench in the first IMD layer; and
forming a single barrier layer and a single metal layer in the two via holes and the trench for forming a metal interconnection and a spin orbit torque (SOT) layer at the same time in the two via holes and the trench, wherein a topmost surface of the SOT layer is even with a top surface of the first IMD layer.
2. The method of claim 1 , further comprising:
forming a magnetic tunneling junction (MTJ) on the SOT layer;
forming a first hard mask on the MTJ;
forming a second hard mask on the first hard mask;
forming a cap layer adjacent to the MTJ; and
forming a second IMD layer around the cap layer.
3. The method of claim 2 , further comprising forming the cap layer on the SOT layer.
4. The method of claim 2 , further comprising forming the second IMD layer on the SOT layer.
5. The method of claim 2 , wherein top surfaces of the first IMD layer and the SOT layer are coplanar.
6. The method of claim 2 , wherein the first hard mask comprises ruthenium (Ru).
7. The method of claim 2 , wherein the second hard mask comprises metal nitride.
8. The method of claim 1 , wherein the metal interconnection and the SOT layer comprise same material.
9. The method of claim 1 , wherein the metal interconnection and the SOT layer comprises tungsten.
10. A semiconductor device, comprising:
a first inter-metal dielectric (IMID) layer on a substrate;
a second IMD layer on the first IMD layer;
a metal interconnection in the second IMD layer;
a third IMD layer on the second IMD layer;
a spin orbit torque (SOT) layer in the third IMD layer, wherein each of the metal interconnection and the SOT layer is made of a single barrier layer and a single metal layer and a topmost surface of the SOT layer is even with a top surface of the third IMD layer;
a magnetic tunneling junction (MTJ) on the SOT layer;
a first hard mask on the MTJ;
a second hard mask on the first hard mask;
a cap layer adjacent to the MTJ; and
a fourth IMD layer around the cap layer.
11. The semiconductor device of claim 10 , wherein bottom surfaces of the third IMD layer and the SOT layer are coplanar.
12. The semiconductor device of claim 10 , wherein the metal interconnection and the SOT layer comprise same material.
13. The semiconductor device of claim 10 , wherein the metal interconnection and the SOT layer comprises tungsten.