Method and apparatus providing multi-planed array memory device
A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.
1. A method, comprising:
identifying an access operation for one or more memory cells that comprises a phase change element in series with a diode;
decoupling, based at least in part on the access operation, a first access circuit from a first electrode line of a first plane of a plurality of parallel planes that is coupled with the diode, wherein the first access circuit is one of a sense circuit or a driver circuit;
coupling, based at least in part on the access operation, a second access circuit with a second electrode line of a second plane of the plurality of parallel planes that is coupled with the phase change element;
coupling, based at least in part on the access operation, a third access circuit with the first electrode line, wherein the third access circuit is the other of the sense circuit or the driver circuit; and
performing the access operation for the one or more memory cells using the coupled second access circuit or the coupled third access circuit.
2. The method of claim 1 , wherein the access operation comprises a write operation,
and wherein the third access circuit comprises the sense circuit, the method further comprising:
coupling the third access circuit with the first electrode line after decoupling the first access circuit, wherein the third access circuit comprises the driver circuit.
3. The method of claim 1 , wherein the access operation comprises a read operation,
and wherein the third access circuit comprises the driver circuit, the method further comprising:
coupling the third access circuit with the first electrode line after decoupling the first access circuit, wherein the third access circuit comprises the sense circuit.
4. The method of claim 1 , wherein at least one of the first electrode line or the second electrode line is shared with one or more second memory cells.
5. The method of claim 1 , further comprising:
decoupling the first access circuit from the first electrode line using a first device; and
decoupling a coupling the third access circuit with the first electrode line using a second device, wherein the first device and the second device are at different terminal ends of the first electrode line.
6. The method of claim 5 , wherein the first device and the second device each comprise a select gate transistor.
7. The method of claim 1 , further comprising:
decoupling the first access circuit from the first electrode line using a first device; and
decoupling a coupling the third access circuit with the first electrode line using the first device, wherein the first access circuit and the third access circuit are at a same terminal end of the first electrode line.
8. The method of claim 7 , wherein the first device comprises a select gate transistor.
9. The method of claim 1 , wherein the first electrode line and the second electrode line are arranged in a cross point architecture.
10. An apparatus, comprising:
one or more memory cells comprising a phase change element in series with a diode;
a first electrode line of a first plane of a plurality of parallel planes coupled with the diode;
a second electrode line of a second plane of the plurality of parallel planes coupled with the phase change element;
a first access circuit selectively couplable with the first electrode line;
a second access circuit selectively couplable with the second electrode line;
a third access circuit selectively couplable with the first electrode line; and
one or more controllers operable to:
identify an access operation for the one or more memory cells;
decouple, based at least in part on identifying the access operation for the one or more memory cells, the first access circuit from the first electrode line, wherein the first access circuit is one of a sense circuit or a driver circuit;
couple, based at least in part on the access operation, the second access circuit with the second electrode line;
couple, based at least in part on the access operation, a third access circuit with the first electrode line, wherein the third access circuit is the other of the sense circuit or the driver circuit; and
perform the access operation for the one or more memory cells using the coupled second access circuit or the coupled third access circuit.
11. The apparatus of claim 10 , wherein the first access circuit comprises the sense circuit, and wherein the one or more controllers are further operable to:
couple the third access circuit with the first electrode line after decoupling the first access circuit, wherein the third access circuit comprises the driver circuit, and wherein the access operation comprises a write operation.
12. The apparatus of claim 10 , wherein the first access circuit comprises the driver circuit, and wherein the one or more controllers are further operable to:
couple the third access circuit with the first electrode line after decoupling the first access circuit, wherein the third access circuit comprises the sense circuit, and wherein the access operation comprises a read operation.
13. The apparatus of claim 10 , wherein at least one of the first electrode line or the second electrode line is shared with one or more second memory cells.
14. The apparatus of claim 10 , further comprising:
a first device at a first terminal end of the first electrode line; and
a second device at a second terminal end of the first electrode line, wherein the one or more controllers are further operable to:
decouple the first access circuit from the first electrode line using the first device; and
couple the third access circuit with the first electrode line using the second device.
15. The apparatus of claim 10 , further comprising:
a first device coupled with the first electrode line, wherein the one or more controllers are further operable to:
decouple the first access circuit from the first electrode line using the first device; and
couple the third access circuit with the first electrode line using the first device, wherein the first access circuit and the third access circuit are at a same terminal end of the first electrode line.
16. An apparatus, comprising:
one or more memory cells comprising a phase change element in series with a diode;
a first electrode line of a first plane of a plurality of parallel planes coupled with the diode;
a second electrode line of a second plane of the plurality of parallel planes coupled with the phase change element;
a first access circuit configured to be decoupled from the first electrode line based at least in part on an access operation for the one or more memory cells, wherein the first access circuit is one of a sense circuit or a driver circuit;
a second access circuit configured to be coupled with the second electrode line based at least in part on the access operation; and
a third access circuit configured to be coupled with the first electrode line based at least in part on the access operation, wherein the third access circuit is the other of the sense circuit or the driver circuit, and wherein the access operation for the one or more memory cells can be performed using the coupled second access circuit or the coupled third access circuit.
17. The apparatus of claim 16 ,
wherein the first access circuit comprises the sense circuit, wherein the third access circuit comprises the driver circuit and is configured to be coupled with the first electrode line after decoupling the first access circuit, and wherein the access operation comprises a write operation.
18. The apparatus of claim 16 ,
wherein the first access circuit comprises the driver circuit, wherein the third access circuit comprises the sense circuit and is configured to be coupled with the first electrode line after decoupling the first access circuit, and wherein the access operation comprises a read operation.
19. The apparatus of claim 16 , further comprising:
a first device configured to decouple the first access circuit from the first electrode line based at least in part on the access operation, the first device at a first terminal end of the first electrode line; and
a second device configured to couple the third access circuit with the first electrode line, the second device at a second terminal end of the first electrode line.
20. The apparatus of claim 16 , further comprising:
a first device configured to decouple the first access circuit from the first electrode line and couple the third access circuit with the first electrode line based at least in part on the access operation, wherein the first access circuit and the third access circuit are at a same terminal end of the first electrode line.