Stacked FET with three-terminal SOT MRAM
View Patent ↗Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.
1. A three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device, comprising:
a first type field effect transistor (FET) that drives an SOT line, wherein the first type FET comprises a write gate in electrical contact with a write wordline (WWL); and
a second type FET in electrical contact with a magnetic tunnel junction (MTJ), wherein the second type FET comprises a read gate in electrical contact with a read wordline (RWL), wherein the first type FET is disposed above the second type FET, and wherein the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.
2. The three-terminal SOT MRAM device of claim 1 , wherein the first type FET comprises an n-type FET (NFET).
3. The three-terminal SOT MRAM device of claim 2 , wherein the second type FET comprises a p-type FET (PFET).
4. The three-terminal SOT MRAM device of claim 1 , wherein the first type FET comprises a PFET.
5. The three-terminal SOT MRAM device of claim 4 , wherein the second type FET comprises an NFET.
6. The three-terminal SOT MRAM device of claim 1 , further comprising:
a substrate; and
an isolation layer disposed between the second type FET and the substrate.
7. The three-terminal SOT MRAM device of claim 6 , wherein the isolation layer comprises a material selected from a group consisting of:
a doped silicon (Si);
an epitaxial doped Si; and
a buried oxide.
8. The three-terminal SOT MRAM device of claim 1 , further comprising:
the SOT line, comprising a heavy metal; and
the MTJ.
9. A three-terminal SOT MRAM device, comprising:
an NFET that drives an SOT line, wherein the NFET comprises a write gate in electrical contact with a WWL; and
a PFET in electrical contact with an MTJ, wherein the PFET comprises a read gate in electrical contact with an RWL, and wherein the PFET is disposed above the NFET.
10. The three-terminal SOT MRAM device of claim 9 , wherein the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.
11. The three-terminal SOT MRAM device of claim 9 , further comprising:
a substrate; and
an isolation layer disposed between the NFET and the substrate.
12. The three-terminal SOT MRAM device of claim 11 , wherein the isolation layer comprises a material selected from a group consisting of:
a doped silicon (Si);
an epitaxial doped Si; and
a buried oxide.
13. A three-terminal SOT MRAM device, comprising:
a PFET that drives an SOT line, wherein the PFET comprises a write gate in electrical contact with a WWL; and
an NFET in electrical contact with an MTJ, wherein the NFET comprises a read gate in electrical contact with an RWL, and wherein the NFET is disposed above the PFET, wherein the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.
14. The three-terminal SOT MRAM device of claim 13 , further comprising:
a substrate; and
an isolation layer disposed between the PFET and the substrate.
15. The three-terminal SOT MRAM device of claim 14 , wherein the isolation layer comprises a material selected from a group consisting of:
a doped silicon (Si);
an epitaxial doped Si; and
a buried oxide.
16. The three-terminal SOT MRAM device of claim 1 , further comprising:
a bonding dielectric; and
a gate cut region, wherein the bonding dielectric and the gate cut region separate the write gate from the read gate.
17. The three-terminal SOT MRAM device of claim 1 , wherein the first type FET comprises a plurality of top nanosheet channels, wherein the second type FET comprise a plurality of bottom nanosheet channels, and wherein the plurality of top nanosheet channels are inline with the plurality of bottom nanosheet channels.
18. The three-terminal SOT MRAM device of claim 1 , wherein SOT line, the WWL, and the RWL are in a same metal level.
19. The three-terminal SOT MRAM device of claim 9 , further comprising a heavy metal layer electrically connected to the SOT line and electrically connected to the MTJ.
20. The three-terminal SOT MRAM device of claim 13 , further comprising a heavy metal layer electrically connected to the SOT line and electrically connected to the MTJ.