Preparation method for semiconductor structure, semiconductor structure and semiconductor memory
A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.
1. A semiconductor structure, comprising:
a substrate;
a bit line structure, a plurality of active pillars, and a word line structure located above the substrate; wherein bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure;
a pillar-shaped conductive structure, located above each active pillar of the active pillars;
a cup-shaped conductive structure, located above the pillar-shaped conductive structure; wherein the cup-shaped conductive structure and the pillar-shaped conductive structure form a lower electrode of the semiconductor structure;
a dielectric layer, located on a surface of the lower electrode; and
an upper electrode, covering a surface of the dielectric layer and filling an electrode gap between adjacent pillar-shaped conductive structure and between adjacent cup-shaped conductive structure,
wherein the upper electrode is opposite to an outer surface of the pillar-shaped conductive structure and an inner surface and an outer surface of the cup-shaped conductive structure, so as to form a capacitor structure.
2. The semiconductor structure of claim 1 , wherein:
the bit line structure is located on the substrate, and the bit line structure extends along a first direction;
the active pillars and the word line structure are located on the bit line structure, and the word line structure extends along a second direction.
3. The semiconductor structure of claim 2 , further comprising a first isolation structure and a bit line gap located in the first isolation structure; wherein the first isolation structure and the bit line structure are formed in a same plane.
4. The semiconductor structure of claim 3 , further comprising a second isolation structure, and the second isolation structure is located above the bit line structure and the first isolation structure; wherein the word line structure is located above the second isolation structure, and there is a word line gap between word line structures.
5. The semiconductor structure of claim 4 , further comprising a third isolation structure; wherein the third isolation structure is located above the word line structure, and a top surface of the third isolation structure and a top surface of the active pillars are located in a same plane.
6. The semiconductor structure of claim 5 , further comprising a gate oxide layer; wherein the gate oxide layer covers a pillar side surface of the active pillars.
7. The semiconductor structure of claim 1 , further comprising: a first support layer located on the active pillars, a second support layer located on top of the pillar-shaped conductive structure, and a third support layer located on top of the cup-shaped conductive structure.
8. The semiconductor structure of claim 7 , wherein a size of a cross section of the cup-shaped conductive structure perpendicular to the extension direction of the cup-shaped conductive structure is greater than a size of a cross section of the pillar-shaped conductive structure perpendicular to the extension direction of the pillar-shaped conductive structure.
9. The semiconductor structure of claim 1 , further comprising a plurality of groups of the pillar-shaped conductive structure and cup-shaped conductive structure which are stacked.
10. A semiconductor memory, comprising a semiconductor structure,
wherein the semiconductor structure comprises:
a substrate;
a bit line structure, a plurality of active pillars, and a word line structure located above the substrate; wherein bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure;
a pillar-shaped conductive structure, located above each active pillar of the active pillars;
a cup-shaped conductive structure, located above the pillar-shaped conductive structure; wherein the cup-shaped conductive structure and the pillar-shaped conductive structure form a lower electrode of the semiconductor structure;
a dielectric layer, located on a surface of the lower electrode; and
an upper electrode, covering a surface of the dielectric layer and filling an electrode gap between adjacent pillar-shaped conductive structure and between adjacent cup-shaped conductive structure,
wherein the upper electrode is opposite to an outer surface of the pillar-shaped conductive structure and an inner surface and an outer surface of the cup-shaped conductive structure, so as to form a capacitor structure.