Resistive random access memory device
A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
1. A memory device, comprising:
a first conductor extending substantially along a first axis;
a first selector material comprising a first portion that extends parallel to a first sidewall of the first conductor and a second portion that extends parallel to a second sidewall of the first conductor; and
a second selector material comprising a third portion that extends along the first sidewall of the first conductor and a fourth portion that extends along the second sidewall of the first conductor, wherein the first and second sidewalls are at least partially embedded in the third and fourth portions, respectively.
2. The memory device of claim 1 , further comprising a first variable resistive material comprising a fifth portion that extends along the first sidewall of the first conductor, wherein the first portion of the first selector material, the third portion of the second selector material, and the fifth portion of the first variable resistive material are stacked along a second axis substantially perpendicular to the first axis.
3. The memory device of claim 2 , wherein at least the first portion of the first selector material and the third portion of the second selector material form a selector device of a first resistive random access memory (RRAM) bit cell, and at least the fifth portion of the first variable resistive material forms a resistor of the first RRAM bit cell that is coupled to the selector device of the first RRAM bit cell in series.
4. The memory device of claim 3 , further comprising a second conductor extending in parallel with a third axis substantially perpendicular to the first axis and the second axis, wherein the first conductor forms a bit line (BL) of the first RRAM bit cell and the second conductor forms a word line (WL) of the first RRAM bit cell.
5. The memory device of claim 3 , further comprising:
a second variable resistive material comprising a sixth portion that extends along the second sidewall of the first conductor; and
a third conductor extending in parallel with a third axis substantially perpendicular to the first axis and the second axis,
wherein the second portion of the first selector material, the fourth portion of the second selector material, and the sixth portion of the second variable resistive material are arranged along the second axis.
6. The memory device of claim 5 , wherein at least the second portion of the first selector material and the fourth portion of the second selector material form a selector device of a second resistive random access memory (RRAM) bit cell, and at least the sixth portion of the second variable resistive material forms a resistor of the second RRAM bit cell that is coupled to the selector device of the second RRAM bit cell in series.
7. The memory device of claim 6 , wherein the first conductor forms a bit line (BL) of the second RRAM bit cell and the third conductor forms a word line (WL) of the second RRAM bit cell.
8. The memory device of claim 5 , wherein the first and second portions of the first selector material, the third and fourth portions of the second selector material, and the fifth and sixth portions of the first and second variable resistive materials, respectively, are respectively mirror symmetric over the first conductor.
9. The memory device of claim 1 , wherein the first conductor is partially embedded in the first selector material.
10. A memory device, comprising:
a first selector material formed on a substrate presenting a first U-shaped profile;
a second selector material formed on the first selector material presenting a second U-shaped profile; and
a first conductor extending in parallel with a first horizontal axis, wherein sidewalls of the first conductor and a lower boundary of the first conductor are partially embedded in the second U-shaped profile.
11. The memory device of claim 10 , further comprising:
a first variable resistive material comprising a portion disposed along a first sidewall portion of the first selector material; and
a second variable resistive material comprising a portion disposed along a second sidewall portion of the first selector material.
12. The memory device of claim 11 , wherein:
a first sidewall portion of the second selector material, the first sidewall portion of the first selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a second horizontal axis substantially perpendicular to the first horizontal axis,
a second sidewall portion of the second selector material, the second sidewall portion of the first selector material, and the portion of the second variable resistive material are arranged along a second direction in parallel with the second horizontal axis, and
at least the first sidewall portion of the first selector material and the first sidewall portion of the second selector material form a selector device of a first resistive random access memory (RRAM) bit cell, and at least the portion of the first variable resistive material forms a resistor of the first RRAM bit cell.
13. The memory device of claim 12 , further comprising:
a second conductor, disposed along the portion of the first variable resistive material, that extends in parallel with a vertical axis, wherein the first conductor forms a bit line (BL) of the first RRAM bit cell and the second conductor forms a word line (WL) of the first RRAM bit cell.
14. The memory device of claim 12 , wherein at least the second sidewall portion of the first selector material and the second sidewall portion of the second selector material form a selector device of a second resistive random access memory (RRAM) bit cell, and at least the portion of the second variable resistive material forms a resistor of the second RRAM bit cell.
15. The memory device of claim 14 , further comprising:
a third conductor, disposed along the portion of the second variable resistive material, that extends in parallel with a vertical axis, wherein the first conductor forms a bit line (BL) of the second RRAM bit cell and the third conductor forms a word line (WL) of the second RRAM bit cell.
16. The memory device of claim 11 , wherein the first and second variable resistive materials each presents a variable resistance value.
17. A method for forming a memory device, comprising:
forming a plurality of dummy patterns on a substrate;
forming a first conductor over the plurality of dummy patterns;
removing the plurality of dummy patterns to form a plurality of openings; and
forming at least a first selector material and a second selector material over the plurality of openings, wherein sidewalls of the first conductor are at least partially embedded in the second selector material.
18. The method of claim 17 , further comprising:
forming a second conductor over the first selector material and the second selector material;
depositing a first capping material on the plurality of dummy patterns;
depositing a variable resistive material on the first capping material; and
depositing a second capping material on the variable resistive material.
19. The method of claim 18 , further comprising:
etching the first capping material, the variable resistive material, and the second capping material to form a plurality of stacked resistor films each extending along a sidewall of a respective one of the plurality of dummy patterns, wherein the first conductor is formed over the plurality of stacked resistor films.
20. The method of claim 18 , wherein the first conductor is configured to serve as a bit line (BL) for the memory device, and the second conductor is configured to serve as word line (WL) for the memory device.