III-N diodes with n-doped wells and capping layers
Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10 17 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.
1. An integrated circuit (IC) device, comprising:
a base;
a semiconductor layer over a portion of the base, wherein the semiconductor layer includes a region of a III-N semiconductor material with n-type dopants at a dopant concentration of at least 5×10 17 dopants per cubic centimeter;
a first electrode interfacing a first portion of the region;
a first capping layer interfacing a second portion of the region, wherein the first capping layer includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter;
a second capping layer between the first capping layer and the second portion of the region, wherein the second capping layer includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter, and a thickness of the second capping layer is between about 2 and 50 nanometers; and
a second electrode, wherein the first capping layer is between the second capping layer and the second electrode.
2. The IC device according to claim 1 , wherein the semiconductor material of the first capping layer is a polarization material.
3. The IC device according to claim 1 , wherein a thickness of the first capping layer is between about 2 and 50 nanometers.
4. The IC device according to claim 1 , wherein the dopant concentration of the semiconductor material of the first capping layer is below 10 16 dopants per cubic centimeter.
5. The IC device according to claim 1 , wherein the dopant concentration of the semiconductor material of the second capping layer is below 10 16 dopants per cubic centimeter.
6. The IC device according to claim 1 , wherein a thickness of the region is between about 50 and 5000 nanometers.
7. The IC device according to claim 1 , wherein the dopant concentration of the n-type dopants of the region is at least 10 18 dopants per cubic centimeter.
8. The IC device according to claim 1 , further including a further III-N semiconductor material between the III-N semiconductor material of the region and the base, wherein the dopant concentration of the further III-N semiconductor material is below 10 17 dopants per cubic centimeter.
9. The IC device according to claim 8 , wherein a thickness of the further III-N semiconductor material is between about 50 and 5000 nanometers.
10. The IC device according to claim 8 , further including a transistor, wherein the transistor includes the further III-N semiconductor material.
11. The IC device according to claim 1 , further including a further material between the semiconductor layer and the base, wherein a band gap of the further material is greater than a band gap of the III-N semiconductor material.
12. The IC device according to claim 1 , wherein a distance between the first portion of the region and the second portion of the region is between about 2 and 500 nanometers.
13. The IC device according to claim 1 , wherein the first capping layer is between the second portion of the region and the second electrode.
14. An integrated circuit (IC) package, comprising:
an IC die comprising an IC device, wherein the IC device includes:
a III-N layer comprising an n-doped well of a III-N semiconductor material with n-type dopants at a dopant concentration of at least 5×10 17 dopants per cubic centimeter,
a cathode over a first portion of the n-doped well,
a capping layer over a second portion of the n-doped well, wherein the capping layer includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter,
an anode, wherein the capping layer is between the second portion of the n-doped well and the anode, and
a III-N transistor over a portion of the III-N layer that includes a III-N semiconductor material with dopants at a dopant concentration below 10 16 dopants per cubic centimeter; and
a further IC component, coupled to the IC die.
15. The IC package according to claim 14 , wherein:
the IC device includes a diode,
the diode includes the n-doped well, the cathode, the anode, and the capping layer, and
the diode is coupled to the III-N transistor.
16. The IC package according to claim 15 , wherein the diode an electrostatic discharge protection diode.
17. A process of making an integrated circuit (IC) device, the process comprising:
providing a semiconductor layer over a base, the semiconductor layer including a region of a III-N semiconductor material with n-type dopants at a dopant concentration of at least 5×10 17 dopants per cubic centimeter;
providing a diode stack structure over a first portion of the region, the diode stack structure including one or more capping layers that include one or more semiconductor materials with a dopant concentration below 10 17 dopants per cubic centimeter;
providing a first electrode, interfacing the diode stack structure so that the one or more capping layers are between the first portion of the region and the first electrode;
providing a second electrode, interfacing a second portion of the region; and
providing a transistor over a portion of the III-N layer that includes the III-N semiconductor material with dopants at a dopant concentration below about 10 16 dopants per cubic centimeter.
18. The process according to claim 17 , wherein providing the semiconductor layer includes:
depositing the III-N semiconductor material over the base, and
providing the region in a portion of the III-N semiconductor material.
19. The process according to claim 17 , wherein the transistor is a III-N transistor.
20. An integrated circuit (IC) device, comprising:
a support structure;
a III-N layer over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material with n-type dopants at a dopant concentration of at least 5×10 17 dopants per cubic centimeter;
a first electrode interfacing a first portion of the n-doped well;
a capping layer interfacing a second portion of the n-doped well, wherein the capping layer includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter, and wherein a distance between the first portion of the n-doped well and the second portion of the n-doped well is between about 2 and 500 nanometers; and
a second electrode, where the capping layer is between the second portion of the n-doped well and the second electrode.
21. The IC device according to claim 20 , wherein:
the capping layer is a first capping layer,
the IC device further includes a second capping layer,
the second capping layer includes a semiconductor material with a dopant concentration below 10 17 dopants per cubic centimeter,
the first capping layer is between the second capping layer and the second electrode, and
the second capping layer is between the first capping layer and the second portion of the n-doped well.
22. The IC device according to claim 21 , wherein a thickness of the second capping layer is between about 2 and 50 nanometers.
23. The IC device according to claim 20 , wherein a thickness of the n-doped well is between about 50 and 5000 nanometers.