IP Library › Granted Patent US 12,400,928
Granted Patent B2
US 12,400,928 · App. 18/739,882 · Granted Aug 26, 2025

Heat dissipation structures

Inventors: Yun-Wei Cheng (Taipei, TW); Chun-Hao Chou (Tainan, TW); Kuo-Cheng Lee (Tainan, TW); Ying-Hao Chen (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L23/367H01L23/481H01L25/0657
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Quick Facts
Patent No.
US 12,400,928
App. No.
18/739,882
Granted
Aug 26, 2025
Kind
B2
Abstract

The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Claims (53)

1. A structure, comprising:

a substrate;

a first dielectric layer disposed on the substrate;

a second dielectric layer disposed on the first dielectric layer;

a heat dissipation layer disposed in the second dielectric layer;

an electrically conductive structure disposed in the first and second dielectric layers and isolated from the heat dissipation layer; and

a thermally conductive structure disposed in the first and second dielectric layers and coupled to the heat dissipation layer.

2. The structure of claim 1 , wherein a portion of the thermally conductive structure is disposed in the substrate.

3. The structure of claim 1 , wherein the thermally conductive structure extends vertically through the substrate and the first and second dielectric layers.

4. The structure of claim 1 , wherein the thermally conductive structure comprises:

a first portion with a first width disposed in the first dielectric layer; and

a second portion with a second width disposed in the second dielectric layer, wherein the second width is smaller than the first width.

5. The structure of claim 1 , wherein the heat dissipation layer comprises an opening, and wherein the electrically conductive structure extends vertically through the opening.

6. The structure of claim 1 , further comprising:

a third dielectric layer disposed on the second dielectric layer; and

a multi-level thermally conductive structure disposed in the third dielectric layer and coupled to the thermally conductive structure.

7. The structure of claim 1 , further comprising:

a third dielectric layer disposed on the second dielectric layer; and

a multi-level electrically conductive structure disposed in the third dielectric layer and coupled to the electrically conductive structure.

8. The structure of claim 1 , further comprising:

a third dielectric layer disposed on the second dielectric layer;

an other heat dissipation layer disposed in the third dielectric layer; and

a multi-level electrically conductive structure disposed in the third dielectric layer and isolated from the other heat dissipation layer.

9. The structure of claim 1 , further comprising:

a third dielectric layer disposed under the second dielectric layer; and

an other heat dissipation layer disposed in the third dielectric layer and coupled to the thermally conductive structure, wherein the other heat dissipation layer comprises:

a first array of heat dissipation stripes aligned along a first direction; and

a second array of heat dissipation stripes disposed on the first array of heat dissipation stripes and aligned along a second direction different from the first direction.

10. The structure of claim 1 , further comprising a heat sink disposed on the second dielectric layer and coupled to the thermally conductive structure.

11. A structure, comprising:

a substrate;

a first metallization layer comprising a first metal line disposed on the substrate;

a second metallization layer comprising a second metal line disposed on the first metallization layer;

a dielectric layer disposed between the first and second metallization layers;

first and second through-vias extending vertically through the substrate, the first metallization layer, and the dielectric layer; and

a thermally conductive line disposed in the dielectric layer and surrounding the first and second through-vias, wherein the thermally conductive line is electrically isolated from the first through-via and is in contact with the second through-via.

12. The structure of claim 11 , wherein the first through-via is electrically coupled to the first and second metal lines.

13. The structure of claim 11 , wherein the second metallization layer further comprises an other thermally conductive line coupled to a top surface of the second through-via.

14. The structure of claim 11 , further comprising:

a first array of thermally conductive lines coupled to the second through-via and aligned along a first direction; and

a second array of thermally conductive lines coupled to the first array of thermally conductive lines and aligned along a second direction different from the first direction.

15. The structure of claim 11 , further comprising a heat sink disposed on the second metallization layer and configured to receive heat from the first metallization layer through the second through-via.

16. The structure of claim 11 , wherein top surfaces of the first and second through-vias are substantially coplanar with each other.

17. A method, comprising:

forming a metallization layer on a first side of a substrate;

depositing a first dielectric layer on a second side of the substrate;

depositing a first thermally conductive layer in an opening in the first dielectric layer;

depositing a second thermally conductive layer on the first thermally conductive layer;

depositing a second dielectric layer on the second thermally conductive layer; and

forming a thermally conductive via through the first dielectric layer, the substrate, and the metallization layer.

18. The method of claim 17 , wherein forming the second thermally conductive layer comprises forming the second thermally conductive layer with elongated sides substantially perpendicular to elongated sides of the first thermally conductive layer.

19. The method of claim 17 , further comprising etching the first dielectric layer to form the opening.

20. The method of claim 17 , further comprising forming a third thermally conductive layer surrounding the thermally conductive via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2024
From: CHENG, YUN-WEI; CHOU, CHUN-HAO; LEE, KUO-CHENG; CHEN, YING-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 067755/0737 →
Continuity (4)
Continuation 18136500 · Apr 19, 2023
Continuation 17107312 · Nov 30, 2020
Continuation 16528207 · Jul 31, 2019
Related Publication 20240332115A1 · Oct 3, 2024
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