IP Library › Granted Patent US 12,400,977
Granted Patent B2
US 12,400,977 · App. 17/664,727 · Granted Aug 26, 2025

Integrated circuit (IC) package employing on-package tunable inductor formed in redistribution layer (RDL) for impedance tuner circuit, and related methods

Inventor: Saravana Maruthamuthu (Bangalore, IN)
Assignee: QUALCOMM INCORPORATED
H01L23/66H01L21/486H01L23/49833H01L23/49838H04B1/0078H04B1/0483H01L21/4857H01L23/49816H01L23/49822H01L24/16H01L2223/6622H01L2223/6672H01L2223/6688H01L2224/16225H01L2924/30101H01L2924/30105H01L2924/30107H01L2924/3011
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Quick Facts
Patent No.
US 12,400,977
App. No.
17/664,727
Granted
Aug 26, 2025
Kind
B2
Abstract

Integrated circuit (IC) package employing on-package tunable inductor formed in redistribution layer (RDL) for impedance tuner circuit, and related methods. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. To reduce the circuit area, the tunable inductor is formed in a RDL of a package substrate of the IC package. The IC package also includes a semiconductor die (“die”) that includes other components of the impedance tuner circuit that are coupled to the tunable inductor by the die being coupled to the package substrate. In this manner, by the tunable inductor being formed in a RDL in the package substrate, the signal path lengths between the tunable inductor and other components of the tunable impedance circuit are reduced, thereby reducing inductance path resistance and improving quality (Q) factor of the tunable inductor.

Claims (109)

1. An integrated circuit (IC) package, comprising:

an impedance tuner circuit, comprising:

a first switch;

a second switch; and

an inductor comprising a first terminal and a second terminal;

a package substrate comprising a first redistribution layer (RDL) and a second RDL, the first RDL comprising the inductor; and

a die coupled to the package substrate, the die comprising:

the first switch; and

the second switch;

the inductor comprising:

a first metal line in the first RDL, the first metal line comprising the first terminal and the second terminal;

a first shunt tap in the first RDL, the first shunt tap coupled to the first terminal and the second terminal;

a second shunt tap in the second RDL;

a first via coupling the second shunt tap to the first terminal; and

a second via coupling the second shunt tap to the second terminal;

the first switch coupled to the first shunt tap; and

the second switch coupled to the second shunt tap.

2. The IC package of claim 1 , wherein the first switch is configured to be closed to shunt the first shunt tap.

3. The IC package of claim 1 , wherein the first switch is configured to be open to provide an open circuit in the first shunt tap.

4. The IC package of claim 1 , wherein:

the first switch comprises a first switch terminal and a second switch terminal;

the first shunt tap comprises:

a first shunt metal line coupled to the first terminal; and

a second shunt metal line coupled to the second terminal; and

the first switch terminal is coupled to the first shunt metal line, and the second switch terminal is coupled to the second shunt metal line.

5. The IC package of claim 4 , wherein:

the first shunt metal line comprises a first end coupled to the first terminal and a second end; and

the second shunt metal line comprises a third end coupled to the second terminal and a fourth end adjacent to the second end.

6. The IC package of claim 4 , wherein:

the first switch terminal is coupled to a first die interconnect of the die;

the second switch terminal is coupled to a second die interconnect of the die;

the first die interconnect is coupled to a first metal interconnect of the package substrate coupled to the first shunt metal line; and

the second die interconnect is coupled to a second metal interconnect of the package substrate coupled to the second shunt metal line.

7. The IC package of claim 6 , wherein:

the package substrate comprises a metallization layer adjacent to the first RDL; and

the metallization layer comprises the first metal interconnect and the second metal interconnect.

8. The IC package of claim 1 , wherein:

the first metal line extends along a first longitudinal axis; and

the first shunt tap extends along a second longitudinal axis parallel to the first longitudinal axis.

9. The IC package of claim 1 , wherein:

the first metal line extends along a first longitudinal axis; and

the first shunt tap extends along a second longitudinal axis orthogonal to the first longitudinal axis.

10. The IC package of claim 1 , wherein:

the second switch comprises a third switch terminal and a fourth switch terminal;

the second shunt tap comprises:

a third shunt metal line coupled to the first terminal; and

a fourth shunt metal line coupled to the second terminal; and

the third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

11. The IC package of claim 1 , wherein:

the second switch comprises a third switch terminal and a fourth switch terminal;

the second shunt tap comprises:

a third shunt metal line coupled to the first terminal; and

a fourth shunt metal line coupled to the second terminal; and

the third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

12. The IC package of claim 1 , wherein:

the first metal line extends along a first longitudinal axis;

the first shunt tap extends along a second longitudinal axis parallel to the first longitudinal axis; and

the second shunt tap extends along a third longitudinal axis that intersects the first longitudinal axis.

13. The IC package of claim 1 , wherein:

the die comprises an active semiconductor layer; and

the first switch is disposed in the active semiconductor layer.

14. The IC package of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server, a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

15. A method of fabricating an integrated circuit (IC) package, comprising:

forming a first switch in a die;

forming a second switch in the die;

forming an inductor in a package substrate, comprising:

forming a first metal line of the inductor in a first redistribution layer (RDL) in the package substrate, the first metal line comprising a first terminal and a second terminal;

forming a first shunt tap of the inductor in the first RDL, the first shunt tap coupled to the first terminal and the second terminal;

forming a second shunt tap in a second RDL in the package substrate, the first shunt tap coupled to the first terminal and the second terminal;

forming a first via coupling the second shunt tap to the first terminal; and

forming a second via coupling the second shunt tap to the second terminal;

coupling the die to the package substrate;

coupling the first switch to the first shunt tap; and

coupling the second switch to the second shunt tap.

16. The method of claim 15 , wherein forming the die comprises:

disposing an active semiconductor layer on a substrate; and

forming the first switch in the active semiconductor layer.

17. The method of claim 16 , further comprising forming the package substrate comprising:

forming a first metal interconnect coupled to a first shunt metal line of the first shunt tap; and

forming a second metal interconnect coupled to a second shunt metal line of the first shunt tap; and

further comprising:

coupling a first die interconnect to a first switch terminal of the first switch;

coupling a second die interconnect to a second switch terminal of the second switch; and

wherein coupling the die to the package substrate comprises:

coupling the first die interconnect to the first metal interconnect; and

coupling the second die interconnect to the second metal interconnect.

18. The method of claim 17 , wherein:

forming the package substrate further comprises forming a metallization layer adjacent to the first RDL;

forming the first metal interconnect comprises forming the first metal interconnect in the metallization layer; and

forming the second metal interconnect comprises forming the second metal interconnect in the metallization layer.

19. The method of claim 15 , wherein:

the first switch comprises a first switch terminal and a second switch terminal;

forming the first shunt tap comprises:

forming a first shunt metal line in the first RDL coupled to the first terminal; and

forming a second shunt metal line in the first RDL coupled to the second terminal; and

coupling the die to the package substrate comprises:

coupling the first switch terminal to the first shunt metal line; and

coupling the second switch terminal to the second shunt metal line.

20. The method of claim 15 , wherein:

forming the second switch comprises forming a third switch terminal and a fourth switch terminal in the die;

forming the second shunt tap comprises:

forming a third shunt metal line in the second RDL coupled to the first terminal; and

forming a fourth shunt metal line in the second RDL coupled to the second terminal; and

coupling the third switch terminal to the third shunt metal line; and

coupling the fourth switch terminal to the fourth shunt metal line.

21. The method of claim 17 , wherein:

forming the first metal line further comprises forming the first metal line extending along a first longitudinal axis;

forming the first shunt tap further comprises forming the first shunt tap extending along a second longitudinal axis parallel to the first longitudinal axis; and

forming the second shunt tap further comprises forming the second shunt tap extending along a third longitudinal axis that intersects the first longitudinal axis.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: MARUTHAMUTHU, SARAVANA
To: QUALCOMM INCORPORATED
Reel/Frame 060117/0069 →
Continuity (1)
Related Publication 20230387044A1 · Nov 30, 2023
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