Semiconductor structure including bit line structure covered by oxide barrier layer and manufacturing method thereof
A semiconductor structure includes a substrate, a bit line structure, an oxide barrier layer, and a bit line capping layer. The bit line structure is disposed on the substrate, in which the bit line structure includes a conductive silicon layer, a conductive layer, and a hard mask layer. The conductive layer is disposed on the conductive silicon layer, in which the conductive layer includes a metal. The hard mask layer is disposed on the conductive layer. The oxide barrier layer is disposed in direct contact with a sidewall of the bit line structure. The bit line capping layer covers the oxide barrier layer.
1. A semiconductor structure, comprising:
a substrate;
a bit line structure disposed on the substrate, wherein the bit line structure comprises:
a conductive silicon layer;
a conductive layer disposed on the conductive silicon layer, wherein the conductive layer comprises a first metal; and
a hard mask layer disposed on the conductive layer,
an oxide barrier layer disposed in direct contact with a first sidewall of the bit line structure and a top surface of the hard mask layer, wherein the oxide barrier layer comprises a first portion in direct contact with the conductive silicon layer, a second portion in direct contact with the conductive layer, and a third portion in direct contact with the hard mask layer, the first portion comprises SiO, SiO 2 , or a combination thereof, the second portion comprises a first oxide of the first metal, the third portion comprises a second oxide of an insulating material of the hard mask layer, the insulating material of the hard mask layer is selected from the group consisting of Si 3 N 4 , SiCN, and SiC, and the first portion, the second portion, and the third portion of the oxide barrier layer are different materials; and
a bit line capping layer covering the oxide barrier layer.
2. The semiconductor structure of claim 1 , further comprising:
a first barrier layer disposed between the conductive silicon layer and the conductive layer, wherein the first barrier layer comprises a second metal, the oxide barrier layer further comprises a fourth portion in direct contact with the first barrier layer, and the fourth portion comprises a third oxide of the second metal.
3. The semiconductor structure of claim 2 , wherein the first barrier layer comprises a metal layer, a metal nitride layer, a metal silicide layer, or combinations thereof.
4. The semiconductor structure of claim 3 , wherein the metal layer comprises a metal selected from the group consisting of Co, Cu, Ni, Ru, Mn, Ag, Au, Pt, Fe, Mo, Rh, Ti, Ta, and W, the metal nitride layer comprises a material selected from the group consisting of tungsten nitride, TiN, and TaN, and the metal silicide layer comprises a material selected from the group consisting of tungsten silicide, tantalum silicide, titanium silicide, molybdenum silicide, zirconium silicide, cobalt silicide, chromium silicide, and nickel silicide.
5. The semiconductor structure of claim 2 , further comprising:
a second barrier layer disposed between the conductive silicon layer and the first barrier layer, wherein the second barrier layer comprises a third metal, the oxide barrier layer further comprises a fifth portion in direct contact with the second barrier layer, and the fifth portion comprises a fourth oxide of the third metal.
6. The semiconductor structure of claim 5 , wherein the first barrier layer is a first metal nitride layer or a metal silicide layer, the second barrier layer is a second metal nitride layer or a metal layer, and the first metal nitride layer and the second metal nitride layer have different materials.
7. The semiconductor structure of claim 5 , further comprising a third barrier layer disposed between the first barrier layer and the conductive layer, wherein the third barrier layer comprises a fourth metal, the oxide barrier layer further comprises a sixth portion in direct contact with the third barrier layer, and the sixth portion comprises a fifth oxide of the fourth metal.
8. The semiconductor structure of claim 7 , wherein the first barrier layer is a metal silicide layer, the second barrier layer is a metal layer or a first metal nitride layer, the third barrier layer is a second metal nitride layer, and the first metal nitride layer and the second metal nitride layer have different materials.
9. The semiconductor structure of claim 1 , wherein the bit line capping layer comprises:
a first nitride layer covering a second sidewall of the oxide barrier layer;
an oxide layer covering a third sidewall of the first nitride layer; and
a second nitride layer covering a fourth sidewall of the oxide layer and a top surface of the bit line structure.
10. The semiconductor structure of claim 1 , wherein the conductive layer comprises a metal selected from the group consisting of W, Ru, Ir, Pt, Rh, and Mo.
11. The semiconductor structure of claim 1 , wherein the bit line capping layer comprises a first nitride layer, an oxide layer, and a second nitride layer covering the oxide barrier layer in sequence, and the first nitride layer and the oxide layer have flush top surfaces.
12. The semiconductor structure of claim 1 , wherein the bit line capping layer comprises a first nitride layer, an oxide layer, and a second nitride layer covering the oxide barrier layer in sequence, and the second nitride layer is in contact with a top portion of the oxide barrier layer.
13. A method of manufacturing a semiconductor structure, comprising:
receiving a bit line structure disposed on a substrate, wherein the bit line structure comprises:
a conductive silicon layer;
a conductive layer disposed on the conductive silicon layer, wherein the conductive layer comprises a first metal; and
a hard mask layer disposed on the conductive layer, wherein the hard mask layer comprises an insulating material selected from the group consisting of Si 3 N 4 , SiCN, and SiC;
performing a plasma treatment on the bit line structure to form an oxide barrier layer in direct contact with a sidewall of the bit line structure and a top surface of the hard mask layer by oxidizing a first surface portion of the conductive silicon layer, a second surface portion of the conductive layer, and a third surface portion of the hard mask layer; and
forming a bit line capping layer covering the oxide barrier layer.
14. The method of claim 13 , wherein the plasma treatment is performed at a temperature between 225° C. and 275° C., and a plasma gas is generated from an oxidizing gas and a reducing gas.
15. The method of claim 14 , wherein a flow rate percentage of the reducing gas is between 30% and 50% in the plasma gas.
16. The method of claim 13 , wherein a treatment time of the plasma treatment is between 20 seconds and 45 seconds.
17. The method of claim 13 , wherein the bit line structure further comprises:
a first barrier layer disposed between the conductive silicon layer and the conductive layer, wherein the first barrier layer comprises a second metal.
18. The method of claim 17 , wherein performing the plasma treatment on the bit line structure further comprises:
oxidizing a fourth surface portion of the first barrier layer.
19. The method of claim 13 , wherein a plasma gas is generated from an oxidizing gas and a reducing gas, and the reducing gas comprises NH 3 .