IP Library Granted Patent US 12,402,413
Granted Patent B2
US 12,402,413 · App. 18/452,910 · Granted Aug 26, 2025

Display device and electronic apparatus with high density pixels

Inventors: Kiwamu Miura (Kanagawa, JP); Naobumi Toyomura (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10D86/481G09F9/30G09G3/20G09G3/3233H05B33/02H10K50/00H10K50/11H10K59/1213H10K59/1216H10K59/123H10K59/8051
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Quick Facts
Patent No.
US 12,402,413
App. No.
18/452,910
Granted
Aug 26, 2025
Kind
B2
Abstract

In a display device including a pixel arranged therein, the pixel including a light emitting unit in which an anode electrode is formed in the uppermost layer of a multilayer wiring structure formed by alternately stacking a plurality of insulating layers and a plurality of wiring layers, and a capacitor element electrically connected to the anode electrode of the light emitting unit, or in an electronic device including the display device, the capacitor element including a first electrode formed in a wiring layer below the anode electrode, a second electrode formed opposite to the first electrode, and attached to the anode electrode of the light emitting unit via a conductive rib, and a first insulating layer interposed between the first electrode and the second electrode.

Claims (29)

1. A display device comprising:

a plurality of pixel circuits arranged in a matrix, wherein each of the pixel circuits includes:

a light emitting element;

a capacitance component;

a sampling transistor configured to supply a data voltage supplied from a data signal line to the capacitance component; and

a drive transistor configured to supply driving current to the light emitting element according to a voltage stored in the capacitance component,

wherein the capacitance component includes a first capacitive element and a second capacitive element connected in parallel to the first capacitive element,

an anode electrode is formed in a first layer,

the first capacitive element includes a first electrode formed in a second layer arranged under the first layer and connected to a gate of the drive transistor, and a second electrode opposed to the first electrode,

the second capacitive element includes a third electrode formed in a third layer arranged under the second layer, and a fourth electrode opposed to the third electrode and connected to the first electrode, and

the second electrode and the third electrode are electrically directly connected to the anode electrode.

2. The display device according to claim 1 , wherein the second electrode is electrically connected to the third electrode.

3. The display device according to claim 1 , wherein the first electrode is electrically connected to the fourth electrode via a plurality of contacts.

4. The display device according to claim 1 , wherein the fourth electrode is formed below the first electrode.

5. The display device according to claim 1 , wherein at least a part of a first region where a gate of the drive transistor is formed overlaps with at least a part of a second region where the first electrode is formed in a plan view.

6. The display device according to claim 1 , wherein at least a part of a first region where a gate of the drive transistor is formed overlaps with at least a part of a third region where the second electrode is formed in a plan view.

7. The display device according to claim 1 , wherein at least a part of a second region where the first electrode is formed overlaps with at least a part of a fourth region where the third electrode is formed in a plan view.

8. The display device according to claim 1 , wherein at least a part of a second region where the first electrode is formed overlaps with at least a part of a fifth region where the fourth electrode is formed in a plan view.

9. The display device according to claim 1 , wherein each of the first capacitive element and the second capacitive element is a MIM (Metal-Insulator-Metal) capacitor.

10. An electronic apparatus comprising the display device according to claim 1 .

11. The electronic apparatus according to claim 10 , wherein the second electrode is electrically connected to the third electrode.

12. The electronic apparatus according to claim 11 , wherein the second electrode and the third electrode are electrically connected to the anode electrode.

13. The electronic apparatus according to claim 10 , wherein the first electrode is electrically connected to the fourth electrode via a plurality of contacts.

14. The electronic apparatus according to claim 10 , wherein the fourth electrode is formed below the first electrode.

15. The electronic apparatus according to claim 10 , wherein at least a part of a first region where a gate of the drive transistor is formed overlaps with at least a part of a second region where the first electrode is formed in a plan view.

16. The electronic apparatus according to claim 10 , wherein at least a part of a first region where a gate of the drive transistor is formed overlaps with at least a part of a third region where the second electrode is formed in a plan view.

17. The electronic apparatus according to claim 10 , wherein at least a part of a second region where the first electrode is formed overlaps with at least a part of a fourth region where the third electrode is formed in a plan view.

18. The electronic apparatus according to claim 10 , wherein at least a part of a second region where the first electrode is formed overlaps with at least a part of a fifth region where the fourth electrode is formed in a plan view.

19. The electronic apparatus according to claim 10 , wherein each of the first capacitive element and the second capacitive element is a MIM (Metal-Insulator-Metal) capacitor.

Priority Claims (1)
JP 2016-174211 · Sep 7, 2016 · national
Continuity (2)
Continuation 16322008
Related Publication 20240032343A1 · Jan 25, 2024
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