Surface uniformity control in pixel structures of image sensors
View Patent ↗A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.
1. A semiconductor device, comprising:
a substrate comprising a top sidewall portion and a bottom sidewall portion;
a dielectric layer disposed on the substrate;
a pixel region comprising a pixel structure, wherein the pixel structure comprises:
an epitaxial structure disposed in the substrate, wherein a sidewall of the epitaxial structure is in physical contact with the bottom sidewall portion of the substrate;
a capping layer disposed on a top surface of the epitaxial structure; and
a barrier layer surrounding the capping layer and disposed on and in physical contact with a substrate region of the substrate that extends above the top surface of the epitaxial structure, wherein the barrier layer comprises an oxide of a material of the substrate region;
an isolation region comprising an isolation structure disposed adjacent to the pixel region; and
a contact pad region comprising a pad structure disposed adjacent to the isolation region.
2. The semiconductor device of claim 1 , wherein a sidewall of the capping layer is spaced apart from a sidewall of the barrier layer by a portion of the dielectric layer.
3. The semiconductor device of claim 1 , wherein a first sidewall portion of the capping layer is in contact with the barrier layer and a second sidewall portion of the capping layer is in contact with the dielectric layer.
4. The semiconductor device of claim 1 , wherein the substrate region comprises the top sidewall portion of the substrate in physical contact with the barrier layer.
5. The semiconductor device of claim 1 , wherein the substrate region comprises a surface portion of the substrate in contact with the dielectric layer.
6. The semiconductor device of claim 1 , wherein the pixel structure further comprises doped regions disposed in the capping layer and the epitaxial structure.
7. The semiconductor device of claim 1 , wherein a first portion of the barrier layer extends along a sidewall of the substrate region and a second portion of the barrier layer extends along a front side surface of the substrate region.
8. The semiconductor device of claim 1 , wherein the dielectric layer is in contact with a front side surface of the capping layer.
9. The semiconductor device of claim 1 , wherein the dielectric layer is in contact with a front side surface of the barrier layer.
10. A semiconductor device, comprising:
a substrate;
a pixel structure, comprising:
a germanium-based epitaxial region disposed in the substrate, wherein sidewalls of the germanium-based epitaxial region is in physical contact with sidewalls of the substrate and wherein a top surface of the germanium-based epitaxial region is below a top surface of the substrate;
a capping layer disposed on the top surface of the germanium-based epitaxial region; and
an oxide layer surrounding the capping layer; and
a doped isolation structure disposed adjacent to the pixel structure.
11. The semiconductor device of claim 10 , wherein the germanium-based epitaxial region comprises a silicon germanium region or a germanium region.
12. The semiconductor device of claim 10 , wherein the capping layer comprises a silicon layer.
13. The semiconductor device of claim 10 , wherein the oxide layer is disposed between a sidewall of the capping layer and a sidewall of the substrate.
14. The semiconductor device of claim 10 , wherein the oxide layer extends from a top surface of the substrate to a sidewall surface of the substrate.
15. The semiconductor device of claim 10 , wherein a top surface of the oxide layer extends above top surfaces of the substrate and the capping layer.
16. The semiconductor device of claim 10 , wherein the pixel structure further comprises:
a p-type doped region disposed in the capping layer; and
an n-type doped region disposed in the capping layer.
17. A semiconductor device, comprising:
a substrate;
a dielectric layer disposed on the substrate;
an epitaxial structure disposed in the substrate;
a barrier layer disposed on a substrate region between the dielectric layer and a top surface of the epitaxial structure, wherein the substrate region extends above a top surface of the epitaxial structure; and
a capping layer disposed on the top surface of the epitaxial structure, wherein a sidewall of the capping layer is spaced apart from a sidewall of the barrier layer by a portion of the dielectric layer.
18. The semiconductor device of claim 17 , wherein the capping layer comprises a silicon layer.
19. The semiconductor device of claim 17 , wherein the epitaxial structure comprises a silicon germanium region or an undoped germanium region.
20. The semiconductor device of claim 17 , wherein the barrier layer surrounds the capping layer.