Granted Patent B2

US 12,405,738 · App. 17/847,300 · Granted Sep 2, 2025

Inventors: Peniel Charles (Bangalore, IN); Venkatesh Doddamane Nagaraj (Bangalore, IN); Amit Pundalik Anchi (Bangalore, IN)

Assignee: Dell Products L.P.

G06F3/064G06F3/0604G06F3/0635G06F3/0659G06F3/0683G06F12/0815

Abstract

Claims (52)

1. An apparatus comprising:

at least one processing device comprising a processor coupled to a memory;

wherein the at least one processing device is configured:

to store a mapping for each of a plurality of logical storage devices of a storage system, the mapping for a given one of the logical storage devices assigning different ranges of logical block addresses of the given logical storage device to respective different cache entities of the storage system;

to receive at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device;

to modify the stored mapping for the given logical storage device based at least in part on the at least one received mapping-related communication; and

to send at least one mapping-related communication to at least one of the first and second host devices based at least in part on the modified stored mapping;

wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that the first host device has generated a new mapping entry;

wherein modifying of the stored mapping for the given logical storage device is controlled based at least in part on results of performance of a consistency check between the new mapping entry and one or more existing mapping entries of the stored mapping; and

wherein the stored mapping is modified to include the new mapping entry responsive to a determination that there is no inconsistency between the new mapping entry and any corresponding existing mapping entry of the stored mapping.

2. The apparatus of claim 1 wherein the at least one processing device comprises an orchestrator device that is separate from the first and second host devices.

3. The apparatus of claim 2 wherein the orchestrator device comprises a multi-path input-output management station coupled to each of the first and second host devices and configured to interact with first and second multi-path input-output drivers of the respective first and second host devices.

4. The apparatus of claim 1 wherein one or more of the cache entities are each assigned multiple distinct ones of the ranges of logical block addresses.

5. The apparatus of claim 1 wherein each of first and second host devices separately stores a version of the mapping for the given logical storage device and accesses its corresponding stored version of the mapping in conjunction with selecting paths for delivery of input-output operations to the storage system.

6. The apparatus of claim 5 wherein selecting paths for delivery of respective input-output operations in a given one of the first and second host devices comprises:

accessing the stored version of the mapping for the given logical storage device; and

for each of at least a subset of the input-output operations:

identifying a particular one of the cache entities based at least in part on a logical block address of the input-output operation and the stored version of the mapping; and

selecting a particular one of a plurality of paths for delivery of the input-output operation to the storage system based at least in part on the identified cache entity.

7. The apparatus of claim 1 wherein the cache entities of the storage system comprise respective components of the storage system that have respective local caches associated therewith.

8. The apparatus of claim 7 wherein the cache entities of the storage system comprise respective storage controllers of the storage system with each such storage controller having a different local cache associated therewith.

9. The apparatus of claim 1 wherein the at least one processing device is further configured:

to determine whether or not the new mapping entry is consistent with a corresponding existing mapping entry of the stored mapping;

responsive to an affirmative determination, to send the mapping-related communication to the first host device with an instruction for the first host device to utilize the new mapping entry;

responsive to a negative determination, to send the mapping-related communication to the first host device with an instruction for the first host device to utilize the corresponding existing mapping entry instead of the new mapping entry.

10. The apparatus of claim 1 wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that all paths from the first host device to a particular cache entity have failed.

11. The apparatus of claim 10 wherein the at least one processing device is further configured:

to determine whether or not at least a threshold number of host devices have each reported that all paths from that host device to the particular cache entity have failed;

responsive to an affirmative determination, to send the mapping-related communication to each of the first host device and one or more other host devices with an instruction for that host device to clear its mapping entry for the particular cache entity and to create a new mapping entry for the particular cache entity;

responsive to a negative determination, to send the mapping-related communication to at least the first host device with an instruction for the first host device to perform one or more tests for detection of a transient failure.

12. The apparatus of claim 1 wherein the receiving, modifying and sending are repeated to ensure that the host devices each maintain a consistent stored version of the mapping for the given logical storage device.

13. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by at least one processing device comprising a processor coupled to a memory, causes the at least one processing device:

to store a mapping for each of a plurality of logical storage devices of a storage system, the mapping for a given one of the logical storage devices assigning different ranges of logical block addresses of the given logical storage device to respective different cache entities of the storage system;

to receive at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device;

to modify the stored mapping for the given logical storage device based at least in part on the at least one received mapping-related communication; and

to send at least one mapping-related communication to at least one of the first and second host devices based at least in part on the modified stored mapping;

wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that the first host device has generated a new mapping entry;

wherein modifying of the stored mapping for the given logical storage device is controlled based at least in part on results of performance of a consistency check between the new mapping entry and one or more existing mapping entries of the stored mapping; and

wherein the stored mapping is modified to include the new mapping entry responsive to a determination that there is no inconsistency between the new mapping entry and any corresponding existing mapping entry of the stored mapping.

14. The computer program product of claim 13 wherein the at least one processing device comprises an orchestrator device that is separate from the first and second host devices.

15. The computer program product of claim 14 wherein the orchestrator device comprises a multi-path input-output management station coupled to each of the first and second host devices and configured to interact with first and second multi-path input-output drivers of the respective first and second host devices.

16. A method comprising:

to store a mapping for each of a plurality of logical storage devices of a storage system, the mapping for a given one of the logical storage devices assigning different ranges of logical block addresses of the given logical storage device to respective different cache entities of the storage system;

to receive at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device;

to modify the stored mapping for the given logical storage device based at least in part on the at least one received mapping-related communication; and

to send at least one mapping-related communication to at least one of the first and second host devices based at least in part on the modified stored mapping;

wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that the first host device has generated a new mapping entry;

wherein modifying of the stored mapping for the given logical storage device is controlled based at least in part on results of performance of a consistency check between the new mapping entry and one or more existing mapping entries of the stored mapping; and

wherein the stored mapping is modified to include the new mapping entry responsive to a determination that there is no inconsistency between the new mapping entry and any corresponding existing mapping entry of the stored mapping.

17. The method of claim 16 wherein the method is performed by at least one processing device that comprises an orchestrator device that is separate from the first and second host devices.

18. The method of claim 17 wherein the orchestrator device comprises a multi-path input-output management station coupled to each of the first and second host devices and configured to interact with first and second multi-path input-output drivers of the respective first and second host devices.

19. The method of claim 16 wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that all paths from the first host device to a particular cache entity have failed.

Assignments (1)

Continuity (1)

References Cited (136)