Bus-interleave protocol to improve multiple logic unit (LUN) operation efficiency

1. A memory device comprising:

a first logic unit (LUN) and a second LUN, wherein the first LUN is coupled to the second LUN, and the first LUN is configured to:

receive a first multi-plane operation command of a set of multi-plane operation commands, wherein the set of multi-plane operation commands corresponds to the first LUN;

latch a first address of the first multi-plane operation command into a first address register of the first LUN;

after receiving the first multi-plane operation command, receive a first operation command, wherein the first operation command corresponds to the second LUN;

after receiving the first operation command, receive a second multi-plane operation command of the set of multi-plane operation commands; and

when receiving the first operation command, keep storing the first address in the first address register.

2. The memory device of claim 1 , wherein the second LUN is configured to:

receive the first operation command; and

latch a second address of the first operation command into a second address register of the second LUN.

3. The memory device of claim 1 , wherein

a first I/O circuit of the first LUN is coupled to a data bus; and

a second I/O circuit of the second LUN is coupled to the data bus.

4. The memory device of claim 1 , wherein the set of multi-plane operation commands comprises a set of multi-plane program operation commands, and the first operation command comprises a single-plane read operation command.

5. The memory device of claim 1 , wherein the first LUN is configured to latch the first address into the first address register by:

sending an enabling signal to a first address counter of the first LUN; and

latching the first address into the first address register based on one or more shift registers of the first address counter.

6. The memory device of claim 5 , wherein the first LUN is configured to send the enabling signal to the first address counter by:

sending the enabling signal to a first shift register of the first address counter in a first cycle; and

passing the enabling signal from the first shift register of the first address counter to a second shift register of the first address counter in a second cycle.

7. The memory device of claim 1 , wherein the first LUN is configured to keep latching the first address into the first address register by:

determining a pending status of the set of multi-plane operation commands; and

in response to determining the pending status, refraining from sending an enabling signal to a first address counter of the first LUN.

8. The memory device of claim 7 , wherein the first LUN is configured to determine the pending status of the set of multi-plane program operation commands by:

determining that the first multi-plane operation command includes a pending multi-plane command.

9. The memory device of claim 1 , wherein the first LUN is further configured to:

determine a standby status of the first LUN; and

latch a third address of the second multi-plane operation command into the first address register.

10. The memory device of claim 9 , wherein the first LUN is further configured to determine the standby status of the first LUN by:

determining that the second multi-plane operation command includes a completion multi-plane command.

11. The memory device of claim 10 , wherein the first LUN is further configured to:

receive a fourth address of a second operation command; and

latch the fourth address into the first address register based on determination of the standby status of the first LUN.

12. The memory device of claim 1 , wherein the first LUN corresponds to a first NAND flash, and the second LUN corresponds to a second NAND flash.

13. A method of operating a memory device, comprising:

receiving a first multi-plane operation command of a set of multi-plane operation commands, wherein the set of multi-plane operation commands corresponds to a first LUN of the memory device;

latching a first address of the first multi-plane operation command into a first address register of the first LUN;

after receiving the first multi-plane operation command, receiving a first operation command, wherein the first operation command corresponds to a second LUN of the memory device;

after receiving the first operation command, receiving a second multi-plane operation command of the set of multi-plane operation commands; and

when receiving the first operation command, keep storing the first address in the first address register.

14. The method of claim 13 , further comprising:

latching a second address of the first operation command into a second address register of the second LUN.

15. The method of claim 13 , wherein latching the first address into the first address register further comprises:

sending an enabling signal to an address counter of the first LUN; and

latching the first address into the first address register based on one or more shift registers of the address counter.

16. The method of claim 15 , wherein keeping storing the first address into the first address register further comprises:

determining a pending status of the set of multi-plane operation commands; and

in response to determining the pending status, refraining from sending an enabling signal to the address counter.

17. The method of claim 16 , wherein determining the pending status of the set of multi-plane operation commands further comprises:

determining that the first multi-plane operation command includes a pending multi-plane command.

18. A memory system, comprising:

a memory controller coupled to a memory device and configured to send a first multi-plane operation command to the memory device, wherein the memory device comprises:

a first logic unit (LUN) and a second LUN, wherein the first LUN is coupled to the second LUN, and the first LUN is configured to:

receive a first multi-plane operation command of a set of multi-plane operation commands, wherein the set of multi-plane operation commands corresponds to the first LUN;

latch a first address of the first multi-plane operation command into a first address register of the first LUN;

after receiving the first multi-plane operation command, receive a first operation command, wherein the first operation command corresponds to the second LUN;

after receiving the first operation command, receive a second multi-plane operation command of the set of multi-plane operation commands; and

when receiving the first operation command, keep storing the first address in the first address register.

19. The memory device of claim 1 , wherein the first LUN is configured to keep storing the first address in the first address register during a time period after receiving the first operation command and before receiving the second multi-plane operation command.

20. The memory device of claim 1 , wherein the first LUN is configured to keep storing the first address in the first address register during a time period after receiving the first multi-plane operation command and before receiving the first operation command.