IP Library › Granted Patent US 12,406,623
Granted Patent B2
US 12,406,623 · App. 18/424,535 · Granted Sep 2, 2025

Display device with overlap layer

Inventors: Myoung Geun Cha (Seoul, KR); Sang Gun Choi (Suwon-si, KR); Ji Yeong Shin (Suwon-si, KR); Yong Su Lee (Seoul, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3233G09G3/32H10K59/123H10K59/131H10K77/111G09G2300/0426G09G2300/0809G09G2320/02H10K2102/311
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Quick Facts
Patent No.
US 12,406,623
App. No.
18/424,535
Granted
Sep 2, 2025
Kind
B2
Abstract

A display device includes a substrate including a display area including a plurality of pixels, a peripheral area around the display area, and a bending area disposed in the peripheral area. A plurality of transistors is disposed in each pixel; a driving voltage line is disposed in the display area and transmits a driving voltage; a driving voltage transmission line is disposed in the peripheral area and is connected to the driving voltage line; and a conductive overlap layer overlaps at least one of the plurality of transistors.

Claims (71)

1. A display device, comprising:

a substrate including a display area including a plurality of pixels, and a peripheral area at least partially surrounding the display area;

a first transistor disposed in each of the plurality of pixels, the first transistor including a semiconductor layer including a channel area;

an overlap layer disposed between the channel area of the first transistor and the substrate in a sectional view, the overlap layer overlapping the channel area of the first transistor in a plan view; and

a driving voltage line disposed over the first transistor in the sectional view and transmitting a driving voltage,

wherein the overlap layer is supplied with the driving voltage through a contact hole which is for electrical connection between the overlap layer and the driving voltage line, and

wherein the contact hole is not disposed in an area of the pixel.

2. The display device of claim 1 , wherein the contact hole is disposed in the peripheral area.

3. The display device of claim 1 , wherein:

the overlap layer includes first portions each overlapping the channel area of the first transistor of the plurality of pixels, and second portions connected to the first portions, and

the first portions and the second portions form a mesh type.

4. The display device of claim 1 , wherein the first transistor is electrically connected to the driving voltage line.

5. The display device of claim 1 , further comprising:

a driving voltage transmission line disposed in the peripheral area and connected to the driving voltage line,

wherein the overlap layer further includes a third portion disposed in the peripheral area, and

wherein the third portion contacts the driving voltage transmission line through the contact hole.

6. The display device of claim 5 , further comprising:

a plurality of insulating layers disposed between the third portion and the driving voltage transmission line,

wherein the contact hole is formed in the plurality of insulating layers.

7. The display device of claim 6 , wherein:

the driving voltage transmission line and the third portion extend in a first direction, and

a plurality of the contact holes are provided along the third portion.

8. The display device of claim 1 , wherein:

the peripheral area includes a bending area, and

the contact hole is disposed between the display area and the bending area.

9. The display device of claim 1 , further comprising:

a scan line that is disposed in the display area, crosses the driving voltage line, and extends in a first direction, and

a pad part disposed in the peripheral area,

wherein the overlap layer comprises a third portion and a fourth portion spaced apart from each other in the peripheral area,

wherein the third portion and the fourth portion are spaced apart from each other with a bending area therebetween, and

wherein the fourth portion is connected to the pad part.

10. The display device of claim 9 , wherein the third portion and the fourth portion extend in a second direction crossing the first direction.

11. A display device, comprising:

a substrate including a display area including a plurality of pixels and for displaying an image, and a peripheral area at least partially surrounding the display area;

a first transistor disposed in each of the plurality of pixels, the first transistor including a semiconductor layer including a channel area;

an overlap layer disposed between the channel area of the first transistor and the substrate in a sectional view, the overlap layer overlapping the channel area of the first transistor in a plan view;

a driving voltage line disposed over the first transistor in the sectional view and transmitting a driving voltage; and

an insulating layer on the overlap layer and in contact with an upper surface of the overlap layer,

wherein the insulating layer does not have any contact hole on the overlap layer in the display area.

12. The display device of claim 11 , wherein:

the overlap layer includes first portions each overlapping the channel area of the first transistor of the plurality of pixels, and second portions connected to the first portions, and

the first portions and the second portions form a mesh type.

13. The display device of claim 11 , wherein the first transistor is electrically connected to the driving voltage line.

14. The display device of claim 11 , wherein the insulating layer has a contact hole disposed on the overlap layer and in the peripheral area.

15. The display device of claim 14 , further comprising:

a driving voltage transmission line disposed in the peripheral area and connected to the driving voltage line,

wherein the overlap layer further includes a third portion disposed in the peripheral area, and

wherein the third portion contacts the driving voltage transmission line through the contact hole.

16. The display device of claim 15 , further comprising:

a plurality of insulating layers disposed between the third portion and the driving voltage transmission line,

wherein the contact hole is formed in the plurality of insulating layers.

17. The display device of claim 16 , wherein:

the driving voltage transmission line and the third portion extend in a first direction, and

a plurality of the contact holes are provided along the third portion.

18. The display device of claim 14 , wherein:

the peripheral area includes a bending area, and

the contact hole is disposed between the display area and the bending area.

19. The display device of claim 11 , further comprising:

a scan line that is disposed in the display area, crosses the driving voltage line, and extends in a first direction, and

a pad part disposed in the peripheral area,

wherein the overlap layer comprises a third portion and a fourth portion spaced apart from each other in the peripheral area,

wherein the third portion and the fourth portion are spaced apart from each other with a bending area therebetween, and

wherein the fourth portion is connected to the pad part.

20. The display device of claim 19 , wherein the third portion and the fourth portion extend in a second direction crossing the first direction.

21. An electronic device, comprising:

a substrate including a display area including a plurality of pixels, and a peripheral area at least partially surrounding the display area;

a first transistor disposed in each of the plurality of pixels, the first transistor including a semiconductor layer including a channel area;

an overlap layer disposed between the channel area of the first transistor and the substrate in a sectional view, the overlap layer overlapping the channel area of the first transistor in a plan view; and

a driving voltage line disposed over the first transistor in the sectional view and transmitting a driving voltage,

wherein the overlap layer is supplied with the driving voltage through a contact hole which is for electrical connection between the overlap layer and the driving voltage line, and

wherein the contact hole is not disposed in an area of the pixel.

Continuity (2)
Continuation 17252670
Related Publication 20240172499A1 · May 23, 2024
References Cited (47)
US 9276051B2 · Sato · 2016 [cited by applicant]
US 9716134B2 · Lin et al. · 2017 [cited by applicant]
US 9910523B2 · Kim et al. · 2018 [cited by applicant]
US 9954043B2 · Park et al. · 2018 [cited by applicant]
US 10025130B2 · Kim et al. · 2018 [cited by applicant]
US 10140039B1 · Earuch et al. · 2018 [cited by applicant]
US 10211277B2 · Lee et al. · 2019 [cited by applicant]
US 10268296B2 · Choi et al. · 2019 [cited by applicant]
US 10444877B2 · Jung et al. · 2019 [cited by applicant]
US 10475868B2 · Park et al. · 2019 [cited by applicant]
US 10483098B2 · Um et al. · 2019 [cited by applicant]
US 10483491B2 · Choi et al. · 2019 [cited by applicant]
US 10528170B2 · Choi et al. · 2020 [cited by applicant]
US 10916616B2 · Lee et al. · 2021 [cited by applicant]
US 10963083B2 · Choi et al. · 2021 [cited by applicant]
US 11036071B2 · Um et al. · 2021 [cited by applicant]
US 11139454B2 · Choi et al. · 2021 [cited by applicant]
US 12082461B2 · Cho · 2024 [cited by examiner]
US 20060250592A1 · Noguchi et al. · 2006 [cited by applicant]
US 20140034923A1 · Kim et al. · 2014 [cited by applicant]
US 20140346473A1 · Park et al. · 2014 [cited by applicant]
US 20160141344A1 · Sato · 2016 [cited by applicant]
US 20160190171A1 · Wang et al. · 2016 [cited by applicant]
US 20160254335A1 · Lee et al. · 2016 [cited by applicant]
US 20160254338A1 · Lin et al. · 2016 [cited by applicant]
US 20170194593A1 · Ma et al. · 2017 [cited by applicant]
US 20170287937A1 · Ka · 2017 [cited by examiner]
US 20220006054A1 · Choi et al. · 2022 [cited by applicant]
US 20220013617A1 · Cha et al. · 2022 [cited by applicant]
US 20230025912A1 · Bae et al. · 2023 [cited by applicant]
JP 2006227586A2 · 2006 [cited by applicant]
JP 4942341 · 2012 [cited by applicant]
KR 1020140018623A · 2014 [cited by applicant]
KR 1020140039617 · 2014 [cited by applicant]
KR 1020140074037A · 2014 [cited by applicant]
KR 1020140137950A · 2014 [cited by applicant]
KR 1020150080257 · 2015 [cited by applicant]
KR 1020150086188A · 2015 [cited by applicant]
KR 1020170049705 · 2017 [cited by applicant]
KR 1020170073482A · 2017 [cited by applicant]
KR 1020170106821 · 2017 [cited by applicant]
KR 1020170080779 · 2017 [cited by applicant]
KR 1020170106591A · 2017 [cited by applicant]
KR 1020170125161A · 2017 [cited by applicant]
KR 1020180049325A · 2018 [cited by applicant]
KR 1020180056497A · 2018 [cited by applicant]
Office Action dated Jul. 4, 2024 issued in the corresponding Korean Patent Application No. 10-2024-0075635. [cited by applicant]