Semiconductor device
A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.
1. A device, comprising:
a transistor channel region;
a transistor gate over the transistor channel region; and
a multilayer gate spacer covering a sidewall of the transistor gate, the multilayer gate spacer comprising:
a first spacer layer on the sidewall of the transistor gate;
a second spacer layer on an outermost sidewall of the first spacer layer;
a third spacer layer on an outermost sidewall of the second spacer layer, wherein when viewed in a cross-sectional view taken along a direction perpendicular to a longitudinal axis of the transistor gate, the third spacer layer has a cross-sectional pattern having a different shape than cross-sectional patterns of the first and second spacer layers, and the cross-sectional pattern of the third spacer layer has a top lower than tops of the cross-sectional patterns of the first and second spacer layers, wherein a bottom of the cross-sectional pattern of the third spacer layer has a horizontal dimension less than a vertical dimension of an outermost side of the cross-sectional pattern of the third spacer layer;
an air-filled region atop the third spacer layer;
a source/drain region adjacent to the transistor channel region; and
a contact etch stop layer over the source/drain region, wherein the contact etch stop layer defines a vertical boundary of the air-filled region, and the contact etch stop layer has a top end level with or higher than a top end of the first spacer layer.
2. The device of claim 1 , wherein the cross-sectional pattern of the third spacer layer is linear-shaped.
3. The device of claim 1 , wherein one or more of the cross-sectional patterns of the first and second spacer layers are L-shaped.
4. The device of claim 1 , wherein the top of the cross-sectional pattern of the third spacer layer is a bottom boundary of an air gap.
5. A device, comprising:
a semiconductor pedestal over a substrate;
a gate structure across the semiconductor pedestal;
a multilayer spacer alongside the gate structure, the multilayer spacer comprising:
a first spacer layer;
a second spacer layer on an outermost sidewall of the second spacer layer; and
a third spacer layer on an outermost sidewall of the second spacer layer;
a capping layer over the multilayer spacer, the capping layer and the third spacer layer defining an air gap between a top of the third spacer layer and a bottom of the capping layer, wherein the bottom of the capping layer in the air gap vertically overlaps with the third spacer layer;
a source/drain region over the semiconductor pedestal; and
a contact etch stop layer over the source/drain region, wherein the contact etch stop layer defines a vertical boundary of the air gap, and the contact etch stop layer has a top end level with or higher than a top end of the first spacer layer.
6. The device of claim 5 , wherein the air gap has a top boundary lower than a top end of first spacer layer.
7. The device of claim 5 , wherein the air gap has a top boundary lower than a top end of the second spacer layer.
8. The device of claim 5 , wherein the air gap has a height greater than a height of the third spacer layer.
9. The device of claim 5 , wherein the top of the third spacer layer is lower than a top of the second spacer layer.
10. The device of claim 5 , wherein the top of the third spacer layer is lower than a top of the first spacer layer.
11. A device, comprising:
a semiconductor fin extending from a substrate;
a gate structure extending across the semiconductor fin; and
a multilayer gate spacer abutting a sidewall of the gate structure, the multilayer gate spacer comprising:
a first spacer layer in contact with the sidewall of the gate structure;
a second spacer layer in contact with a sidewall of the first spacer layer oriented away from the gate structure;
a third spacer layer in contact with a sidewall of the second spacer layer oriented away from the second spacer layer; and
an air-filled region atop the third spacer layer;
a source/drain region over the semiconductor fin; and
a contact etch stop layer over the source/drain region, wherein the contact etch stop layer defines a vertical boundary of the air-filled region, and the contact etch stop layer has a top end not lower than a top end of the first spacer layer.
12. The device of claim 11 , further comprising:
a dielectric layer defining a top boundary of the air-filled region.
13. The device of claim 11 , wherein the air-filled region has a top boundary lower than a top of the second spacer layer.
14. The device of claim 11 , wherein the air-filled region has a top boundary lower than a top of the first spacer layer.
15. The device of claim 11 , wherein the second spacer layer defines another vertical boundary of the air-filled region.
16. The device of claim 11 , wherein the third spacer layer has a linear patter in a cross-sectional view.
17. The device of claim 11 , wherein the first spacer layer has an L-shaped pattern in a cross-sectional view.
18. The device of claim 11 , wherein the second spacer layer has an L-shaped region in a cross-sectional view.
19. The device of claim 11 , wherein the third spacer layer includes a material different from a material of the second spacer layer and a material of the first spacer layer.
20. The device of claim 1 , wherein the horizontal dimension of the bottom of the cross-sectional pattern of the third spacer layer is the same as a horizontal dimension of the top of the cross-sectional pattern of the third spacer layer.