Integrated circuit, method for forming a layout of integrated circuit using standard cells
A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.
1. An integrated circuit layout, comprising:
a power rail and a ground rail extending in parallel along a first direction and respectively having a narrow portion connected to a wide portion;
a first standard cell between the narrow portions of the power rail and the ground rail; and
a second standard cell between the wide portions of the power rail and the ground rail and abutted to a side of the first standard cell, wherein the first standard cell and the second standard cell respectively comprise:
an upper edge overlapping the power rail, a lower edge overlapping the ground rail, and a well boundary between the upper edge and the lower edge;
two active regions of opposite conductivity types at two sides of the well boundary; and
a gate line extending between the upper edge and the lower edge along a second direction and intersecting the two active regions, wherein the first direction and the second direction are perpendicular,
wherein a first cell height between the upper edge and lower edge of the first standard cell and a second cell height between the upper edge and lower edge of the second standard cell are different, the well boundaries of the first standard cell and the second standard cell are aligned along the first direction.
2. The integrated circuit layout according to claim 1 , wherein a centerline between the upper edge and the lower edge of the first standard cell and a centerline between the upper edge and the lower edge of the second standard cell are aligned along the first direction.
3. The integrated circuit layout according to claim 2 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are overlapped.
4. The layout according to claim 2 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are not overlapped.
5. The integrated circuit layout according to claim 1 , wherein a distance between the narrow portion of the power rail and an edge of the active regions of the first standard cell close to the narrow portion and a distance between the wide portion of the power rail and an edge of the active regions of the second standard cell close to the wide portion are the same.
6. The integrated circuit layout according to claim 1 , wherein the upper edge of the first standard cell overlaps a centerline of the narrow portion of the power rail, the lower edge of the first standard cell overlaps a centerline of the narrow portion of the ground rail.
7. The integrated circuit layout according to claim 1 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent to the well boundary are aligned along the first direction.
8. The integrated circuit layout according to claim 1 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent to the well boundary are offset along the first direction.
9. The integrated circuit layout according to claim 1 , further comprising:
a first conductive connector extending from an edge of the narrow portion of the power rail along the second direction a first length to partially overlap one of the active regions of the first standard cell; and
a second conductive connector extending from an edge of wide portion of the power rail a second length to partially overlap one of the active regions of the second standard cell,
wherein the first length and the second length are different.
10. The integrated circuit layout according to claim 1 , further comprising:
a first dummy gate line at a side of the first standard cell opposite to the second standard cell;
a second dummy gate line at a side of the second standard cell opposite to the second standard cell; and
a third dummy gate line between the first standard cell and the second standard cell, wherein the first dummy gate line and the third dummy gate line have line ends flush with line ends of the gate line of the first standard cell, the second dummy gate line has line ends flush with line ends of the gate line of the second standard cell.