Integrated circuit
An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.
1. An integrated circuit, comprising:
a first transistor of a first conductivity type comprising a first active area extending in a first direction;
a second transistor of the first conductivity type comprising at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and
a third transistor of a second conductivity type that is stacked on the second transistor and comprises at least two third active areas arranged above the at least two second active areas, wherein a top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view,
wherein the third transistor is separated from the first transistor and the second transistor along the first direction in the layout view.
2. The integrated circuit of claim 1 , wherein the first conductivity type is N type, and the second conductivity type is P type.
3. The integrated circuit of claim 1 , wherein the first transistor further comprises a fourth active area separate from the first active area in a second direction different from the first direction.
4. The integrated circuit of claim 3 , wherein a cell height of a first cell including the first transistor is equal to a cell height of a second cell including the second and third transistors.
5. The integrated circuit of claim 3 , wherein a bottom most boundary line of the fourth active area is aligned with a bottom most boundary line of one of the at least two third active areas in the layout view.
6. The integrated circuit of claim 1 , wherein a cell height of a first cell including the first transistor is different from a cell height of a second cell including the second and third transistors.
7. The integrated circuit of claim 1 , further comprising:
a fourth transistor of the second conductivity type that is stacked on the first transistor and comprises a fourth active area extending in the first direction and a second gate stripe extending in a second direction different from the first direction to pass across the fourth active area.
8. The integrated circuit of claim 7 , further comprising:
fifth and sixth transistors of different conductivity types in a first cell, wherein the fifth and sixth transistors comprise a plurality of fifth active areas overlapping each other in the layout view,
wherein the second and third transistors are included in a second cell abutting the first cell in the second direction,
wherein the first gate stripe further crosses at least one in the plurality of fifth active areas.
9. An integrated circuit, comprising:
a first cell having a first cell height and comprising a first active area in a first layer;
a second cell having a second cell height different from the first cell height, wherein the second cell comprises a first plurality of active areas in the first layer; and
a third cell having a third cell height greater than the first cell height and the second cell height, wherein the third cell comprises a second plurality of active areas in a second layer below the first layer;
wherein the first and second cells abut the third cell in a first direction, and the first and second cells abut each other in a second direction,
wherein the first active area and a first area in the second plurality of active areas align with each other along the first direction, and
first and second areas in the first plurality of active areas align with second and third areas in the second plurality of active areas along the first direction.
10. The integrated circuit of claim 9 , wherein the first cell height is smaller than the second cell height and the third cell height.
11. The integrated circuit of claim 9 , wherein a number of the first plurality of active areas is smaller than a number of the second plurality of active areas.
12. The integrated circuit of claim 9 , wherein the second cell further comprises:
a third plurality of active areas in the second layer, wherein the third plurality of active areas overlap the first plurality of active areas, and align with corresponding ones of the second plurality of active areas in a layout view.
13. The integrated circuit of claim 9 , wherein the second cell further comprises a non-doped region between the first and second areas in the first plurality of active areas, and
a third area in the second plurality of active areas is disposed between the second and third areas in the second plurality of active areas.
14. The integrated circuit of claim 9 , wherein the first active area aligns with a fourth area in the second plurality of active areas along the first direction.
15. The integrated circuit of claim 9 , further comprising:
a plurality of gate stripes that extend continuously in the second direction and shared by the first and second cells.
16. A method, comprising:
forming a first plurality of active areas that extend in a first row, wherein one of the first plurality of active areas overlaps another one of the first plurality of active areas in a layout view;
forming a second plurality of active areas that extend in a second row, wherein one of the second plurality of active areas overlaps another one of the second plurality of active areas in the layout view;
forming a third plurality of active areas that extend in a third row between the first and second rows, wherein a length of one in the third plurality of active areas and a length of one in the second plurality of active areas are different from each other; and
forming a plurality of gate structures extending to cross at least one of the first plurality of active areas, at least one of the second plurality of active areas, and at least one of the third plurality of active areas.
17. The method of claim 16 , wherein two overlapping active areas have different conductivity types.
18. The method of claim 16 , wherein the third plurality of active areas are shorter than the first plurality of active areas and the second plurality of active areas.
19. The method of claim 16 , wherein one of the third plurality of active areas overlaps another one of the third plurality of active areas in the layout view.
20. The method of claim 16 , further comprising:
forming a fourth plurality of active areas that extend in a fourth row adjacent to the second row, wherein one of the fourth plurality of active areas overlaps another one of the fourth plurality of active areas in the layout view,
wherein the third and fourth plurality of active areas are shorter than the first plurality of active areas and the second plurality of active areas.