IP Library Granted Patent US 12,408,519
Granted Patent B2
US 12,408,519 · App. 17/565,925 · Granted Sep 2, 2025

Display apparatus and method of manufacturing the same

Inventors: Junhee Lee (Hwaseong-si, KR); Kiseong Seo (Seoul, KR); Deok Hoi Kim (Seongnam-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/126H10K59/131H10K77/111H10K59/1201
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,408,519
App. No.
17/565,925
Granted
Sep 2, 2025
Kind
B2
Abstract

A display apparatus includes a base substrate including a display area and a peripheral area, a conductive layer formed on the base substrate in an entirety of the peripheral area and the display area, a buffer layer on the conductive layer, a thin film transistor on the buffer layer in the display area, an electrode in a contact hole that is formed through the buffer layer to expose a side surface of the conductive layer in the peripheral area, the electrode making contact the conductive layer, an insulating pattern in the contact hole on the electrode, and a wiring on the insulating pattern and electrically connected to the electrode.

Claims (36)

1. A method of manufacturing a display apparatus, the method comprising:

forming a conductive layer on a base substrate;

forming a buffer layer on the conductive layer;

forming an active pattern on the buffer layer;

forming an insulating layer on the active pattern;

forming a contact hole by partially removing the insulating layer and the buffer layer to expose the conductive layer;

forming an electrode that contacts the conductive layer in the contact hole;

forming an insulating pattern on the electrode so as to expose a portion of the electrode with a portion of the insulating pattern disposed in the contact hole; and

forming a wiring on the insulating pattern, the wiring being electrically connected to the electrode.

2. The method as claimed in claim 1 , wherein the conductive layer is an n+ doped amorphous silicon layer.

3. The method as claimed in claim 1 , further comprising:

forming a gate electrode on the insulating layer before forming the contact hole; and

forming an interlayer insulating layer on the gate electrode,

wherein in forming the contact hole, the contact hole is formed by partially removing the interlayer insulating layer, the insulating layer, and the buffer layer.

4. The method as claimed in claim 1 , wherein in forming the contact hole, a portion of the conductive layer is removed so as to penetrate completely through the conductive layer such that a side surface of the conductive layer is exposed, and

the side surface of the conductive layer directly contacts the electrode.

5. The method as claimed in claim 4 , wherein the electrode directly contacts the side surface of the conductive layer in the contact hole.

6. The method as claimed in claim 1 , wherein the base substrate includes at least one polyimide layer and at least one barrier film layer.

7. A method of manufacturing a display apparatus, the method comprising:

forming a conductive layer on a base substrate;

forming a buffer layer on the conductive layer;

forming an active pattern on the buffer layer;

forming an insulating layer on the active pattern;

forming a contact hole by partially removing the insulating layer, the buffer layer, and the conductive layer;

forming an electrode that contacts the conductive layer in the contact hole;

forming an insulating pattern on the electrode so as to expose a portion of the electrode; and

forming a wiring on the insulating pattern, the wiring directly connected to the electrode both at one location at a first side of the contact hole and at a second location spaced apart from the first side of the contact hole.

8. The method as claimed in claim 7 , wherein

in forming the contact hole, a portion of the conductive layer is removed so as to penetrate completely through the conductive layer such that a side surface of the conductive layer is exposed, and

the side surface of the conductive layer directly contacts the electrode in the contact hole.

9. The method as claimed in claim 8 , wherein the wiring makes direct contact with both a top surface of the electrode and a side surface of the electrode.

10. The method as claimed in claim 7 , wherein the wiring makes direct contact with both a top surface of the electrode and a side surface of the electrode.

11. The method as claimed in claim 7 , wherein a portion of the insulating pattern is in the contact hole.

12. The method as claimed in claim 7 , wherein

in forming the contact hole, a portion of the substrate is removed such that a side surface of the conductive layer is exposed, and

the side surface of the conductive layer directly contacts the electrode in the contact hole.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2021
From: LEE, JUNHEE; SEO, KISEONG; KIM, DEOK HOI
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 058508/0820 →
Priority Claims (1)
KR 10-2018-0149132 · Nov 28, 2018 · national
Continuity (2)
Division 16592138 · Oct 3, 2019
Related Publication 20220123085A1 · Apr 21, 2022
References Cited (33)
US 7727823B2 · Jeong et al. · 2010 [cited by applicant]
US 9356087B1 · Lee · 2016 [cited by examiner]
US 10192896B2 · Kim et al. · 2019 [cited by applicant]
US 20120146886A1 · Minami · 2012 [cited by examiner]
US 20140117342A1 · Kwon · 2014 [cited by examiner]
US 20140167050A1 · Jin · 2014 [cited by examiner]
US 20140217397A1 · Kwak · 2014 [cited by examiner]
US 20150379923A1 · Lee et al. · 2015 [cited by applicant]
US 20160179229A1 · Ahn · 2016 [cited by examiner]
US 20160181345A1 · Lee · 2016 [cited by examiner]
US 20170170206A1 · Lee · 2017 [cited by examiner]
US 20170263887A1 · Han · 2017 [cited by examiner]
US 20170287938A1 · Lee · 2017 [cited by examiner]
US 20180048055A1 · O'Driscoll et al. · 2018 [cited by applicant]
US 20180315809A1 · Kim et al. · 2018 [cited by applicant]
CN 103794628 · 2014 [cited by applicant]
CN 106887447 · 2017 [cited by applicant]
CN 107180595 · 2017 [cited by applicant]
EP 3182473 · 2017 [cited by applicant]
EP 3392921 · 2018 [cited by applicant]
JP 2014107242 · 2014 [cited by applicant]
KR 1020060109655 · 2006 [cited by applicant]
KR 1020110085904 · 2011 [cited by applicant]
KR 1020160001584 · 2016 [cited by applicant]
KR 1020160049173 · 2016 [cited by applicant]
KR 1020160084549 · 2016 [cited by applicant]
KR 1020170121392 · 2017 [cited by applicant]
KR 1020170135550 · 2017 [cited by applicant]
KR 1020180024909 · 2018 [cited by applicant]
Extended European Search Report corresponding to European Application or Patent No. 19211800.8 dated May 6, 2020. [cited by applicant]
Chinese Office Action, with English Translation, for Chinese Patent Application No. 201911177383.9, dated Feb. 3, 2024. [cited by applicant]
Korean Notice of Allowance with English translation for Korean Patent Application No. 10-2018-0149132, dated Sep. 30, 2024. [cited by applicant]
Korean Office Action, with English Translation, for Korean Application No. 10-2018-0149132, dated Oct. 23, 2023. [cited by applicant]
Cited By (2)
US 12,666,782 US 12,684,925