Method and system for latch-up prevention
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
1. A method, comprising:
providing a cell library defining a plurality of functional cells configured to perform a predefined function and a plurality of tap cells;
receiving an integrated circuit design;
selecting a plurality of the functional cells from the cell library based on the integrated circuit design;
arranging the plurality of the functional cells into a floor plan, wherein the floor plan includes a plurality of rows;
arranging a plurality of the tap cells into predetermined locations of the floor plan;
modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan; and
determining potential latchup locations in the floor plan based on the voltage droop of the floor plan.
2. The method of claim 1 , wherein the floor plan includes at least one row that contains only tap cells.
3. The method of claim 1 , wherein determining potential latchup locations in the floor plan based on the voltage droop of the floor plan includes determining whether the voltage droop exceeds a predetermined value.
4. The method of claim 1 , further comprising modifying the arrangement of at least one of the functional cells or the tap cells based on the determined potential latchup locations.
5. The method of claim 4 , wherein modifying the arrangement includes moving selected ones of the tap cells to different locations in the floor plan.
6. The method of claim 4 , wherein modifying the arrangement includes adding additional tap cells to the floor plan.
7. The method of claim 4 , wherein modifying the arrangement includes moving selected ones of the functional cells to different locations in the floor plan.
8. The method of claim 4 , further comprising:
relocating at least some of the plurality of the tap cells arranged into the floor plan based on the determined potential latchup locations.
9. A method, comprising:
selecting a plurality of functional cells, configured to perform predefined functions, from a cell library based on an integrated circuit design;
arranging the plurality of functional cells into a floor plan;
arranging a plurality of tap cells from the cell library into locations of the floor plan;
modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan; and
determining potential latchup locations in the floor plan based on the voltage droop of the floor plan.
10. The method of claim 9 , wherein the floor plan includes at least one row that contains only tap cells.
11. The method of claim 9 , wherein determining potential latchup locations in the floor plan based on the voltage droop of the floor plan includes determining whether the voltage droop exceeds a predetermined value.
12. The method of claim 9 , further comprising modifying the arrangement of at least one of the functional cells or the tap cells based on the determined potential latchup locations.
13. The method of claim 12 , wherein modifying the arrangement includes moving selected ones of the tap cells to different locations in the floor plan.
14. The method of claim 12 , wherein modifying the arrangement includes adding additional tap cells to the floor plan.
15. The method of claim 12 , wherein modifying the arrangement includes moving selected ones of the functional cells to different locations in the floor plan.
16. The method of claim 9 , further comprising:
relocating at least some of the plurality of tap cells arranged into the floor plan based on the determined potential latchup locations.
17. A method, comprising:
selecting a plurality of functional cells, configured to perform predefined functions, from a cell library based on an integrated circuit design;
arranging the plurality of functional cells into a floor plan;
arranging a plurality of tap cells from the cell library into locations of the floor plan;
modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan; and
determining potential latchup locations in the floor plan based on the voltage droop of the floor plan and determining whether the voltage droop exceeds a predetermined value.
18. The method of claim 17 , wherein the floor plan includes at least one row that contains only tap cells.
19. The method of claim 17 , further comprising modifying the arrangement of at least one of the functional cells or the tap cells based on the determined potential latchup locations.
20. The method of claim 17 , further comprising:
relocating at least some of the plurality of tap cells arranged into the floor plan based on the determined potential latchup locations.