Atom probe tomography specimen preparation
View Patent ↗The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam (“FIB”) microscopes is then conducted to shape the bump structures into APT specimen.
1. A structure, comprising:
a wafer having a semiconductor structure over a substrate;
a trench on a surface of the semiconductor structure;
a bank structure surrounding the trench;
a sample structure in the trench, the sample structure including a portion of the semiconductor structure, a tip portion of the sample structure including a first surface roughness that is finer than a second surface roughness of a lower portion of the sample structure, the tip portion and the lower portion including different materials, the lower portion including a portion of the substrate.
2. The structure of claim 1 , wherein the sample structure is integrally included on the substrate.
3. The structure of claim 1 , wherein the tip portion of the sample structure is substantially at a same level as or lower than an upper surface of the bank structure with respect to the substrate.
4. The structure of claim 1 , wherein the sample structure includes a portion of the substrate.
5. The structure of claim 1 , wherein the second surface roughness ranges from about 50 nm to about 200 nm, inclusive.
6. The structure of claim 1 , wherein the first surface roughness is finer than about 10 nm.
7. The structure of claim 1 , wherein the tip portion of the sample structure is needle-shaped over the lower portion of the sample structure.
8. A device, comprising:
a substrate;
a semiconductor structure over the substrate;
a trench in the semiconductor structure;
a cone-shaped bump structure in the trench, the bump structure including an upper portion and a lower portion, the upper portion and the lower portion including different materials, the lower portion including a portion of the substrate; and
a bank structure surrounding the trench.
9. The device of claim 8 , wherein the upper portion is thinner than the lower portion.
10. The device of claim 8 , wherein the upper portion includes a finer surface roughness than the lower portion.
11. The device of claim 8 , wherein the lower portion includes a surface roughness ranging between about 50 nm to about 200 nm, inclusive.
12. The device of claim 8 , wherein the upper portion includes a surface roughness finer than about 10 nm.
13. The device of claim 8 , wherein an upper end of the upper portion is substantially at a same level as an upper surface of the bank structure.
14. The device of claim 8 , wherein an upper end of the upper portion is lower than an upper surface of the bank structure.
15. The device of claim 8 , wherein a top surface of the upper portion includes a diameter ranging between about 8 nm to about 50 nm, inclusive.