Laser driver incorporating clamping circuit with freewheeling diode
View Patent ↗An input is coupled to a cathode of a laser diode having its anode coupled to a high-voltage-supply, with a cascoded current mirror having an input and output branches. The input branch is coupled between the high-voltage-supply and a sense resistor coupled to the input. The output branch is coupled between the high-voltage-supply and an output. A sense resistance is coupled between the output and ground, and includes a diode-coupled transistor coupled to the output and a resistor coupled between the diode-coupled transistor and ground. The input branch generates a current proportional to a voltage across the laser diode, and the output branch generates a mirrored current proportional to the current proportional to the voltage across the laser diode. A voltage proportional to the voltage across the laser diode is generated by the mirrored current flowing through the sense resistance. A comparison circuit compares this voltage to a threshold.
1. A circuit, comprising:
an input node configured to be coupled to a cathode of a laser diode having its anode coupled to a high voltage supply node;
a cascoded current mirror having an input branch and an output branch, wherein the input branch is coupled between the high voltage supply node and a sense resistor coupled to the input node, and wherein the output branch is coupled between the high voltage supply node and an output node;
a sense circuit coupled between the output node and ground, wherein the sense circuit comprises a diode coupled transistor coupled to the output node and a resistor coupled between the diode coupled transistor and a ground node;
wherein the input branch is configured to generate a current proportional to a voltage drop across the laser diode;
wherein the output branch is configured to generate a mirrored current proportional to the current proportional to the voltage drop across the laser diode;
wherein a voltage proportional to the voltage drop across the laser diode is generated as a result of the mirrored current flowing through the sense resistor; and
a comparison circuit configured to compare the voltage proportional to the voltage drop across the laser diode to a threshold voltage.
2. The circuit of claim 1 , wherein the comparison circuit is configured to assert a fault output if the voltage proportional to the voltage drop across the laser diode exceeds the threshold voltage for a set period of time.
3. The circuit of claim 2 , wherein the set period of time is at least equal to an expected duration of a laser drive current pulse.
4. The circuit of claim 1 , wherein the comparison circuit is configured to assert a fault flag if the voltage proportional to the voltage drop across the laser diode exceeds the threshold voltage.
5. The circuit of claim 1 , further comprising a bias setting current configured to bias cascode transistors of the cascoded current mirror.
6. The circuit of claim 1 , further comprising clamp circuits configured to protect transistors of the cascoded current mirror against damage.
7. A circuit, comprising:
a cascoded current mirror having an input branch and an output branch;
a first sense resistor coupled between the input branch and an input node, wherein the input node is configured to be coupled to a cathode of a laser diode having its anode coupled to a high voltage supply node;
an output node coupled to the output branch;
a sense branch coupled between the output node and a ground node; and
a comparator having a first input coupled to the output node, a second input coupled to a threshold voltage, and an output configured to generate a fault flag.
8. The circuit of claim 7 , wherein the cascoded current mirror comprises:
a first transistor having a drain coupled to the first sense resistor, a source, and a gate;
a second transistor having a drain coupled to the source of the first transistor, a source coupled to the high voltage supply node, and a gate coupled to the drain of the first transistor to define a diode configuration;
a third transistor having a source coupled to the high voltage supply node, a drain, and a gate coupled to the gate of the second transistor; and
a fourth transistor having a source coupled to the drain of the third transistor, a drain coupled to the output node, and a gate coupled to the gate of the first transistor.
9. The circuit of claim 8 , further comprising:
a first Zener diode having an anode coupled to the source of the first transistor and the drain of the second transistor, and a cathode coupled to the high voltage supply node;
a second Zener diode having an anode coupled to the gates of the second and third transistors, and a cathode coupled to the high voltage supply node;
a third Zener diode having an anode coupled to the source of the fourth transistor and the drain of the third transistor, and a cathode coupled to the high voltage supply node; and
a fourth Zener diode having an anode coupled to the gates of the first and fourth transistors, and a cathode coupled to the high voltage supply node.
10. The circuit of claim 8 , further comprising a bias setting circuit, the bias setting circuit comprising:
a fifth transistor having a drain coupled to the gates of the first and fourth transistors, a source coupled to the drain of the first transistor, and a gate directly coupled to the drain of the fifth transistor and indirectly coupled to the source of the fifth transistor through a capacitor; and
a current source generating a bias current received by the drain of the fifth transistor.
11. The circuit of claim 7 , wherein the sense branch comprises:
a diode coupled transistor having a source coupled to the output node, a drain, and a gate coupled to the drain of the diode coupled transistor; and
a second sense resistor coupled between the drain of the diode coupled transistor and ground.
12. The circuit of claim 11 , further comprising a fifth Zener diode having an anode coupled to a ground node, and a cathode coupled to the output node.
13. The circuit of claim 7 , further comprising a digital circuit, wherein the digital circuit comprises:
a delay circuit configured to receive the fault flag and to output a delayed version of the fault flag;
an AND gate having a first input configured to receive the fault flag, a second input configured to receive the delayed version of the fault flag, and an output configured to generate a clock pulse; and
a flip flop having a data input coupled to a supply voltage, a clock input coupled to the output of the AND gate, a clear input coupled to a fault clear signal, and an output generating a fault output signal.
14. A method of detecting faults in driving of a laser diode, the method comprising:
when a voltage proportional to a voltage drop across the laser diode rises and remains above a threshold voltage for a period of time greater than an expected duration of a laser drive current pulse, indicating detection of a fault in the driving of the laser diode.
15. The method of claim 14 , further comprising, prior to indicating, comparing the voltage proportional to the voltage drop across the laser diode to the threshold voltage.
16. The method of claim 14 , further comprising generating the voltage proportional to the voltage drop across the laser diode.
17. The method of claim 16 , wherein generating the voltage proportional to the voltage drop across the laser diode comprises:
generating a current proportional to the voltage drop across the laser diode;
mirroring the current proportional to the voltage drop across the laser diode, across a cascoded current mirror, to produce a mirrored current; and
generating the voltage proportional to the voltage drop across the laser diode as being equal to a voltage drop of the mirrored current across a voltage replication circuit.
18. The method of claim 14 , further comprising receiving external input setting the threshold voltage and setting the period of time.