Semiconductor device with different sized epitaxial structures
An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.
1. An apparatus, comprising:
a first gate structure of a core device on a substrate;
a first L-shaped spacer over a sidewall of the first gate structure and a portion of the substrate adjacent to the first gate structure;
a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate structure by the first L-shaped spacer;
a second gate structure of an I/O device on the substrate;
a second L-shaped spacer over a sidewall of the second gate structure and a portion of the substrate adjacent to the second gate structure; and
a second raised S/D structure on the substrate and spaced apart from the second gate structure by the second L-shaped spacer,
wherein a spacer width of the first L-shaped spacer is the same as a spacer width of the second L-shaped spacer, and
wherein a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.
2. The apparatus of claim 1 , wherein sidewalls of the first S/D structure are ( 111 ) faces, and a top surface of the first S/D structure is a ( 100 ) face.
3. The apparatus of claim 2 , wherein sidewalls and a top surface of the second S/D structure are rounded.
4. The apparatus of claim 2 , wherein transitions between the sidewalls of the first S/D structure and the top surface of the first S/D structure are angled corners between the ( 111 ) faces and the ( 100 ) face, and transitions between the sidewalls of the second S/D structure and the top surface of the second S/D structure are rounded corners.
5. The apparatus of claim 1 , wherein the substrate is a fully depleted silicon-on-insulator (SOI) substrate.
6. The apparatus of claim 1 , wherein a channel material of the first gate structure is silicon germanium, and a channel material of the second gate structure is silicon.
7. The apparatus of claim 1 , wherein a thickness of a gate dielectric of the first gate structure is less than a thickness of a gate dielectric of the second gate structure.
8. The apparatus of claim 1 , wherein the first and second raised S/D structures are epitaxial semiconductor structures.
9. The apparatus of claim 1 , wherein the first and second raised S/D structures are epitaxial structures, the first raised S/D structure has faceted side and top faces, and the second raised S/D structure has an etched top and sides.
10. The apparatus of claim 1 , wherein a distance between the first gate structure and a base of the first raised S/D structure is the same as a distance between the second gate structure and a base of the second gate structure.
11. A method comprising:
forming a first gate structure of a core device and a second gate structure of an I/O device on a substrate;
forming a first L-shaped spacer over a sidewall of the first gate structure and a portion of the substrate adjacent to the first gate structure;
forming a second L-shaped spacer over a sidewall of the second gate structure and a portion of the substrate adjacent to the second gate structure, the second L-shaped spacer having the same spacer width as the first L-shaped spacer;
forming a first raised source/drain (S/D) structure spaced apart from the first gate structure by the first L-shaped spacer;
forming a second raised S/D structure spaced apart from the second gate structure by the second L-shaped spacer; and
etching the second raised S/D structure,
wherein the etching causes a distance between the first gate structure and a sidewall of the first S/D structure to be greater than a distance between the second gate structure and a sidewall of the second S/D structure.
12. The method of claim 11 , wherein a material of the first raised S/D structure is different from a material of the second raised S/D structure.
13. The method of claim 11 , wherein sidewalls of the first S/D structure are ( 111 ) faces, and a top surface of the first S/D structure is a ( 100 ) face.
14. The method of claim 11 , wherein the substrate is a fully depleted silicon-on-insulator (SOI) substrate.
15. The method of claim 11 , wherein a channel material of the first gate structure is silicon germanium, and a channel material of the second gate structure is silicon.
16. The method of claim 11 , wherein a thickness of a gate dielectric of the first gate structure is less than a thickness of a gate dielectric of the second gate structure.
17. The method of claim 11 , wherein a distance between the first gate structure and a base of the first raised S/D structure is the same as a distance between the second gate structure and a base of the second gate structure.
18. An electronic device comprising:
a core device including:
a first gate structure on a substrate;
a first L-shaped spacer over a sidewall of the first gate structure and a portion of the substrate adjacent to the first gate structure; and
a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate structure by the first L-shaped spacer,
an I/O device including:
a second gate structure on the substrate;
a second L-shaped spacer over a sidewall of the second gate structure and a portion of the substrate adjacent to the second gate structure; and
a second raised source/drain (S/D) structure on the substrate and spaced apart from the second gate structure by the second L-shaped spacer,
wherein a spacer width of the first L-shaped spacer is the same as a spacer width of the second L-shaped spacer,
wherein a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.
19. The electronic device of claim 18 , wherein sidewalls of the first S/D structure are ( 111 ) faces, and a top surface of the first S/D structure is a ( 100 ) face.
20. The electronic device of claim 18 , wherein the first and second raised S/D structures are epitaxial structures, the first raised S/D structure has faceted side and top faces, and the second raised S/D structure has etched sides.